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HD404829R Series
AS Microcomputer Incorporating a LCD controller/Driver Circuit
ADE-202-057C Rev.4 Sept. 1999 Description
The HD404829R series incorporates an 8-bit A/D converter (four channels), a Liquid Crystal Display (LCD) and a serial interface, and has large-current Input/Output (I/O) pins. The series is a 4-bit single-chip microcomputer best used in the AV equipment such as CD radio cassette tape recorders which require the LCD display control. The HD404829R Series, with a 32.768kHz sub-oscillator for clocks, counts up the system clock and a variety of power modes can reduce power consumption. The HD4074829 is a ZTAT TM microcomputer which incorporates a PROM. System development period has been dramatically reduced so that the process from debugging to mass production is smooth. (The PROM programming specifications are the same as those for Type 27256.) ZTAT TM: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
* 1,876-digit x 4-bit RAM * 44 I/O pins, including 10 high-current pins (15 mA, max.) and 20 pins multiplexed with LCD segment pins * Four timer/counters * 8-bit input capture circuit * Three timer outputs (including two PWM out-puts) * Two event counter inputs (including one double-edge function) * Clock-synchronous 8-bit serial interface * A/D converter (4 channels x 8 bits) * LCD controller/driver (52 segments x 4 commons) * Built-in oscillators Main clock: 4.2-MHz ceramic (an external clock is also possible) Subclock: 32.768-kHz crystal * Eleven interrupt sources Five by external sources, including three double-edge functions
HD404829R Series
Six by internal sources * Subroutine stack up to 16 levels, including interrupts * Four low-power dissipation modes Subactive mode Standby mode Watch mode Stop mode * One external input for transition from stop mode to active mode * Instruction cycle time (min.): 0.95 s (fOSC = 4.2 MHz) * Operation voltage VCC = 2.7 V to 6.0 V (HD404829R) VCC = 2.7 V to 5.5 V (HD4074829) * Two operating modes MCU mode MCU/PROM mode (HD4074829 only)
2
HD404829R Series
Ordering Information
Type Mask ROM Product Name HD404828R Model Name HD404828RH HD404828RFS HD404828RTF HD4048212R HD4048212RH HD4048212RFS HD4048212RTF HD404829R HD404829RH HD404829RFS HD404829RTF ZTAT
TM
ROM (Words) 8,192
Package 100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B)
12,288
100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B)
16,384
100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B)
HD4074829
HD4074829H HD4074829FS HD4074829TF
16,384
100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B)
Caution about operation!
It has been confirmed that the HD404829R Series, same as the ZTAT TM version HD4074829 and the conventional HD404829 Series, satisfies the electrical properties given on the data sheets, etc. However, effective values of the electrical properties, the operating margin, and the noise margin may differ with the manufacturing processes, on-chip ROM, and layout patterns. Therefore, conduct an evaluation test of your system using the ZTATTM version and the mask ROM version. Also conduct a similar evaluation test for checkup before replacing your conventional product with the HD404829R Series.
3
HD404829R Series
List of Functions
Product name ROM (Words) RAM (Digits) I/O Large-current I/O pins LCD segment multiplexed pins Timer / Counter Input capture Timer output Event input Serial interface A/D converter LCD controller / driver circuit Interrupts External Internal Low-Power Dissipation Mode Stop mode Watch mode Standby mode Subactive mode Main Oscillator Ceramic oscillation Crystal oscillation Sub oscillator Crystal oscillation HD404828R 8,192 HD4048212R 12,288 1,876 44 (max) 10 (Sink 15 mA max) 20 4 8 bit x 1 3 (PWM output possible for 2) 2 (edge selection possible for 1) 1 (8-bit syncronous) 8 bit x 4 channels Max. 52 seg x 4 com 5 (edge selection possible for 3) 6 4 O O O O O (0.4-4.2MHz) O (0.4-4.2MHz) O (32.768 kHz) 0.95 s (f OSC = 4.2 MHz) 2.7 to 6.0 100-pin plastic QFP (FP-100B) 100-pin plastic QFP (FP-100A) 100-pin plastic TQFP (TFP-100B) Guaranteed operation temperature (C) -20 to +75 2.7 to 5.5 -- HD404829R 16,384 HD4074829 16,384PROM
Minimum instruction execution time Operating voltage (V) Package
4
Pin Arrangement
AVCC AN 0 AN 1 AN 2 AN 3 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 /STOPC D11 /INT0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
FP-100B TFP-100B
Top view
R00 /INT1 R01 /INT2 R02 /INT3 R03 /INT4 R10 /TOB R11 /TOC R12 /TOD R13 /EVNB R20 /EVND R21 /SCK R22 /SI R23 /SO R30 /SEG1 R31 /SEG2 R32 /SEG3 R33 /SEG4 R40 /SEG5 R41 /SEG6 R42 /SEG7 R43 /SEG8 R50 /SEG9 R51 /SEG10 R52 /SEG11 R53 /SEG12 R60 /SEG13
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NUMG NUMO NUMO VCC V3 V2 V1 COM4 COM3 COM2 COM1 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39
SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R73 /SEG20 R72 /SEG19 R71 /SEG18 R70 /SEG17 R63 /SEG16 R62 /SEG15 R61 /SEG14
HD404829R Series
5
HD404829R Series
Pin Arrangement
NUMO V CC V3 V2 V1 COM4 COM3 COM2 COM1 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NUMO NUMG AV CC AN 0 AN 1 AN 2 AN 3 AV SS TEST OSC 1 OSC 2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 /STOPC D11 /INT 0 R00 /INT 1 R01 /INT 2 R02 /INT 3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
FP-100A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 R7 3 /SEG20 R7 2 /SEG19 R7 1 /SEG18 R7 0 /SEG17 R6 3 /SEG16 R6 2 /SEG15 R6 1 /SEG14 R6 0 /SEG13 R5 3 /SEG12
6
R03 /INT 4 R10 /TOB R11 /TOC R12 /TOD R13 /EVNB R2 0 /EVND R21 /SCK R22 /SI R23 /SO R3 0 /SEG1 R3 1 /SEG2 R3 2 /SEG3 R3 3 /SEG4 R4 0 /SEG5 R4 1 /SEG6 R4 2 /SEG7 R4 3 /SEG8 R5 0 /SEG9 R5 1 /SEG10 R5 2 /SEG11
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Top view
HD404829R Series
Pin Description
Pin Number Item Power supply Test Reset Oscillator Symbol VCC GND TEST RESET OSC1 OSC2 FP-100B TFP-100B 97 13 7 10 8 9 FP-100A 99 15 9 12 10 11 I I I O I/O Function Applies power voltage Connected to ground Used for factory testing only: Connect this pin to V CC Resets the MCU Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator ,crystal oscillator or connect OSC 1 to an external oscillator curcuit Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open. Input/output pins addressed by individual bits; pins D0-D9 are high-current pins that can each supply up to 15 mA Input pins addressable by individual bits Input/output pins addressable in 4-bit units Input pins for external interrupts Input pin for transition from stop mode to active mode Serial interface clock input/output pin Serial interface receive data input pin Serial interface transmit data output pin Timer output pins Event count input pins Power pins for LCD controller/driver; may be left open during operation since they are connected by internal voltage division resistors. Voltage conditions are: VCC V1 V2 V3 GND O O Common signal pins for LCD Segment signal pins for LCD
X1 X2 Port D0-D9
11 12 14-23
13 14 16-25
I O I/O
D10 , D11 R00-R7 3 Interrupt Stop clear Serial interface INT0, INT1, INT2-INT4 STOPC SCK SI SO Timer TOB, TOC, TOD EVNB, EVND LCD V1, V2, V3
24, 25 26-57 25-29 24 35 36 37 30-32 33, 34 94-96
26, 27 28-59 27-31 26 37 38 39 32-34 35, 36 96-98
I I/O I I I/O I O O I
COM1-COM4 SEG1-SEG52
90-93 38-89
92-95 40-91
7
HD404829R Series
Pin Number Item A/D converter Symbol AV CC FP-100B TFP-100B 1 FP-100A 3 I/O Function Power pin for A/D converter: Connect it to the same potential as V CC, as physically close to the V CC pin as possible Ground for AVCC: Connect it to the same potential as GND, as physically close to the GND pin as possible I Analog input pins for A/D converter These are not pins for user applications. Connect NUMG to the same potential as GND. Leave NUMO open.
AV SS
6
8
AN0-AN 3 NUMG NUMO NUMG NUMO
2-5 100 98,99
4-7 2 100,1
8
HD404829R Series
Block Diagram
RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND
HMCS400 CPU
ROM INT0 INT1 INT2 INT3 INT4
RAM
External interrupt control circuit R0 Port
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D Port
Timer A 8-bit free-running timer
R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R73
EVNB TOB
Timer B 8-bit free-running / reload timer
TOC
Timer C 8-bit free-running / reload timer
EVND TOD
Timer D 8-bit free-running / reload timer
SCK SI SO AVcc AVss AN0 AN1 AN2 AN3 V1 V2 V3 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3
Clock-synchronous 8-bit serial interface
A/D converter 4 channels x 8 bits
LCD controller / driver circuit 52 segments x 4 commons
SEG52
R7 Port
R6 Port
R5 Port
R4 Port
R3 Port
R2 Port
R1 Port
~
~
: High current pins
9
HD404829R Series
Memory Map
ROM Memory Map The ROM memory map is shown in figure 1 and described below.
ROM address $0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern (4096 words) $0FFF $1000 ROM address $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction $0009 (jump to timer B, INT 2 routine) $000A JMPL instruction $000B (jump to timer C, INT 3 routine) $000C JMPL instruction $000D (jump to timer D, INT 4 routine) $000E JMPL instruction (jump to A/D, serial routine) $000F
HD404828R Program (8,192 words) HD4048212R Program (12,288 words) HD404829R, HD4074829 Program (16,384 words)
$1FFF $2000
$2FFF $3000
$3FFF
Figure 1 ROM Memory Map Vector Address Area ($0000-$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000-$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000-$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$1FFF: HD404828R; $0000-$2FFF: HD4048212R; $0000-$3FFF; HD404829R, HD4074829): Used for program coding.
10
HD404829R Series
RAM Memory Map The MCU contains a 1,876-digit x 4-bit RAM area consisting of a memory register area, an LCD data area, a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above areas. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000-$03F): * Interrupt Control Bits Area ($000-$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. * Special Function Register Area ($004-$01F, $024-$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, LCD, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for the LCD control register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other registers. * Register Flag Area ($020-$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
11
HD404829R Series
RAM address $000 RAM-mapped registers $040 $050 LCD display area (52 digits) $084 $090 Not used Memory registers (16 digits) RAM address $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Interrupt control bits area Port mode register A (PMRA) Serial mode register A (SMRA) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C1 (TMC1) Timer C (TRCL/TWCL) (TRCU/TWCU) Timer mode register D1 (TMD1) Timer D (TRDL/TWDL) (TRDU/TWDU) Timer mode register B2 Timer mode register C2 Timer mode register D2 A/D mode register A/D data register lower A/D data register upper Not used $01B $01C $01D $01E $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $03E $03F LCD control register LCD mode register LCD output register 1 LCD output register 2 LCD output register 3 (LCR) (LMR) (LOR1) (LOR2) (LOR3) W W W W W (TMB2) (TMC2) (TMD2) (AMR) (ADRL) (ADRU) W W R/W R/W W W R/W R/W W W R/W R/W W R/W R/W R/W R/W R/W W R R
*2
Data (464 digits x 3) V = 0 (bank 0) V = 1 (bank 1) V = 2 (bank 2)
*1
$260 Data (352 digits) $3C0 Stack (64 digits) $3FF
$090 Data (464 digits) V=0 (bank = 0) $25F Data (464 digits) V=1 (bank = 1) Data (464 digits) V=2 (bank = 2)
Register flag area Port mode register B Port mode register C (PMRB) (PMRC) W W W W W W
Detection edge select register 1 (ESR1) Detection edge select register 2 (ESR2)
Notes: 1. The data area has three banks: bank 0 (V = 0) to bank 2 (V = 2). 2. Two registers are mapped on the same area. R: Read only W: Write only R/W: Read/write
Serial mode register B (SMRB) System clock select register (SSR) Not used Port D0-D3 DCR Port D4-D7 DCR Port D8 and D9 DCR Not used Port R0 DCR Port R1 DCR Port R2 DCR Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Not used V register (V) (DCD0) (DCD1) (DCD2) (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) (DCR5) (DCR6) (DCR7)
W W W W W W W W W W W
R/W
10 11 14 15 17 18
Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00A Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00B Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00E Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W $00F Timer read register D lower (TRDL) R Timer write register D lower (TWDL) W $011 Timer read register D upper (TRDU) R Timer write register D upper (TWDU) W $012
Figure 2 RAM Memory Map
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HD404829R Series
RAM address $000
Bit 3 IM0 (IM of INT0)
Bit 2
Bit 1
Bit 0
IE (Interrupt enable flag)
IF0 (IF of INT0)
RSP (Reset SP bit)
$001
IMTA (IM of timer A)
IMTC (IM of timer C) IMAD (IM of A/D)
IFTA (IF of timer A) IFTC (IF of timer C)
IM1 (IM of INT1)
IMTB (IM of timer B) IMTD (IM of timer D)
IF1 (IF of INT1)
IFTB (IF of timer B)
IFTD (IF of timer D)
$002
$003
IFAD (IF of A/D)
Interrupt control bits area
Bit 3
$020 DTON (Direct transfer on flag)
Bit 2
ADSF (A/D start flag)
Bit 1
WDON (Watchdog on flag)
Bit 0
LSON (Low speed on flag)
$021
RAME (RAM enable flag)
Not used
ICEF (Input capture error flag)
ICSF (Input capture status flag)
$022
IM3 (IM of INT3)
IMS (IM of serial interface)
IF3 (IF of INT3)
IFS (IF of serial interface)
IM2 (IM of INT2)
IM4 (IM of INT4)
IF2 (IF of INT2)
IF4 (IF of INT4)
$023
IF: IM: IE: SP:
Interrupt request flag Interrupt mask Interrupt enable flag Stack pointer
Register flag area
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD IE IM LSON IF ICSF ICEF RAME RSP WDON ADSF DTON Not used Allowed REM/REMD Allowed TM/TMD Allowed
Not executed Not executed Allowed Allowed Not executed in active mode Used in subactive mode Not executed
Allowed Allowed Not executed Inhibited Allowed Not executed
Allowed Inhibited Inhibited Allowed Allowed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instuction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
13
HD404829R Series
Bit 3 $000 Interrupt control bits area $003 PMRA $004 SMRA $005 SRL $006 SRU $007 TMA $008 TMB1 $009 TRBL/TWBL $00A TRBU/TWBU $00B MIS $00C TMC1 $00D TRCL/TWCL $00E TRCU/TWCU $00F TMD1 $010 TRDL/TWDL $011 TRDU/TWDU $012 TMB2 $013 TMC2 $014 TMD2 $015 AMR $016 ADRL $017 ADRU $018 Not used Not used *4 *2 *3 *2 *1 *2 Not used R21/SCK Not used R22/SI R23/SO Serial transmit clock speed selection Serial data register (lower digit) Serial data register (upper digit) Clock source setting (timer A) Clock source setting (timer B) Timer B register (lower digit) Timer B register (upper digit) R23 /SO PMOS control Interrupt frame period selection Clock source setting (timer C) Timer C register (lower digit) Timer C register (upper digit) Clock source setting (timer D) Timer D register (lower digit) Timer D register (upper digit) Not used Timer-B output mode selection Timer-C output mode setting Timer-D output mode setting *5 Not used Bit 2 Bit 1 Bit 0
Analog channel selection
A/D data register (lower digit) A/D data register (upper digit) Not used
LCR $01B
Not used
*6
*7
R31/SEG2 R41/SEG6
*8 R30/SEG1 R40/SEG5
LMR $01C LCD input clock source selection R33/SEG4 R32/SEG3 LOR1 $01D LOR2 $01E LOR3 $01F $020 R43/SEG8 Not used R42/SEG7
LCD duty cycle selection
R7/SEG17-20 R6/SEG13-16 R5/SEG9-12 Register flag area
$023 PMRB $024 PMRC $025 ESR1 $026 R03/INT4 D11/INT0 R02/INT3 D10/STOPC R01/INT2 R20/EVND R00/INT1 R13/EVNB
INT3 detection edge selection INT2 detection edge selection
ESR2 $027 EVND detection edge selection INT4 detection edge selection *9 * 10 SMRB $028 Not used Not used SSR $029 * 11 * 12 Not used DCD0 $02C DCD1 $02D DCD2 $02E DCR0 $030 DCR1 $031 DCR2 $032 DCR3 $033 DCR4 $034 DCR5 $035 DCR6 $036 DCR7 $037 Port D3 DCR Port D2 DCR Port D7 DCR Port D6 DCR Not used Not used Port D1 DCR Port D0 DCR Port D5 DCR Port D4 DCR Port D9 DCR Port D8 DCR * 13 Not used
Not used Port R03 DCR Port R02 DCR Port R01 DCR Port R00 DCR Port R13 DCR Port R12 DCR Port R11 DCR Port R10 DCR Port R23 DCR Port R22 DCR Port R21 DCR Port R20 DCR Port R33 DCR Port R32 DCR Port R31 DCR Port R30 DCR Port R43 DCR Port R42 DCR Port R41 DCR Port R40 DCR Port R53 DCR Port R52 DCR Port R51 DCR Port R50 DCR Port R63 DCR Port R62 DCR Port R61 DCR Port R60 DCR Port R73 DCR Port R72 DCR Port R71 DCR Port R70 DCR Not used V $03F Not used Not used Bank 0 to bank 2 selection Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Timer-A/time-base Auto-reload on/off Pull-up MOS control Input capture selection A/D conversion time Display on/off in watch mode LCD power switch LCD display on/off SO idle H/L setting Transmit clock source selection 32-kHz oscillation stop setting 32-kHz oscillation division ratio System clock selection
Figure 5 Special Function Register Area
14
HD404829R Series
Memory Register (MR) Area ($040-$04F): Consisting of 16 addresses, this area (MR0-MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 1023 Level 1 960
$3C0
Bit 3 $3FC $3FD $3FE $3FF $3FF ST PC 10 CA PC 3
Bit 2 PC13 PC9 PC6 PC2
Bit 1 PC 12 PC 8 PC 5 PC 1
Bit 0 PC11 PC7 PC4 PC0
PC13 -PC0 : Program counter ST: Status flag CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
15
HD404829R Series
LCD Data Area ($050-$083): Used for storing 52-digit LCD data which is automatically output to LCD segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to the LCD description for details. Data Area ($090-$3BF): 464 digits from $090 to $25F have three banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $260 to $3BF is accessed without setting the bank register.
Bank register (V: $03F) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W V1 0 0 R/W V0
Not used Not used
V1 0
V0 0 1
Bank area selection Bank 0 is selected Bank 1 is selected Bank 2 is selected Not used
1
0 1
Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. If V1 = 1 and V0 = 1, no bank is selected, and the operation is not guaranteed.
Figure 7 Bank Register (V) Stack Area ($3C0-$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
16
HD404829R Series
Functional Description
Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below.
3 Accumulator Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W (B) 1 W register Initial value: Undefined, R/W 3 X register Initial value: Undefined, R/W 3 Y register Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W 3 SPY register Initial value: Undefined, R/W (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Initial value: 1, R/W not possible 13 (PC) 9 Stack pointer Initial value: $3FF, R/W not possible 1 1 1 1 5 (SP) 0 (ST) 0 (SPX) 0 (Y) 0 (X) 0 0 (W) 0 (A) 0 0
Program counter Initial value: $0000, R/W not possible
Figure 8 Registers and Flags Accumulator (A) and B Register (B) A and B are 4-bit registers, and are used to hold the results of ALU(arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers. W Register (W), X Register (X), Y Register (Y) W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing.
17
HD404829R Series
SPX Register (SPX) and SPY Register (SPY) The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA) CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR.) During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. Status Flag (ST) ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. Program Counter (PC) The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP) The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD. Reset The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one t RC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles. Initial values after MCU reset are listed in table 1.
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HD404829R Series
Table 1 Initial Values After MCU Reset
Item Program counter Status flag Stack pointer Interrupt flags/mask Interrupt enable flag Interrupt request flag Interrupt mask I/O Port data register Data control register Abbr. (PC) Initial Value $0000 Contents Indicates program execution point from start address of ROM area (ST) (SP) (IE) (IF) (IM) (PDR) (DCD0, DCD1) (DCD2) (DCR0, -DCR7) Port mode register A Port mode register B Port mode register C bits 3, 1, 0 Detection edge select register 1 Detection edge select register 2 Timer/ counters, serial interface Timer mode register A Timer mode register B1 Timer mode register B2 Timer mode register C1 Timer mode register C2 Timer mode register D1 Timer mode register D2 Serial mode register A Serial mode register B Prescaler S Prescaler W Timer counter A Timer counter B Timer counter C Timer counter D (PMRA) (PMRB) (PMRC3, PMRC1, PMRC0) (ESR1) (ESR2) (TMA) (TMB1) (TMB2) (TMC1) (TMC2) (TMD1) (TMD2) (SMRA) (SMRB) (PSS) (PSW) (TCA) (TCB) (TCC) (TCD) 1 $3FF 0 0 1 All bits 1 All bits 0 - - 00 All bits 0 - - 00 0000 000 Refer to description of port mode register A Refer to description of port mode register B Refer to description of port mode register C Enables conditional branching Stack level 0 Inhibits all interrupts Indicates there is no interrupt request Prevents (masks) interrupt requests Enables output at level 1 Turns output buffer off (to high impedance)
0000 0000 0000 0000 - - 00 0000 - 000 0000 0000 0000 - - x0 $000 $00 $00 $00 $00 $00
Disables edge detection Disables edge detection Refer to description of timer mode register A Refer to description of timer mode register B1 Refer to description of timer mode register B2 Refer to description of timer mode register C1 Refer to description of timer mode register C2 Refer to description of timer mode register D1 Refer to description of timer mode register D2 Refer to description of serial mode register A Refer to description of serial mode register B -- -- -- -- -- --
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HD404829R Series
Table 1 Initial Values After MCU Reset (cont)
Initial Value $X0 $X0 $X0 000 00 - 0 $80 - 000 0000 0000 0000 - 000 0 0 0 0 0 0 0000 000 - - 00 Refer to description of operating modes Refer to description of timer C Refer to description of A/D converter Refer to description of operating modes Refer to description of timer D Refer to description of timer D Refer to description of operating modes, I/O, and serial interface Refer to description of operating modes and oscillation circuits Refer to description of RAM memory map
Item Timer/ counters, serial interface Timer write register B Timer write register C Timer write register D Octal counter A/D A/D mode register A/D data register LCD LCD control register LCD mode register LCD output register 1 LCD output register 2 LCD output register 3 Bit registers Low speed on flag Watchdog timer on flag A/D start flag Direct transfer on flag Input capture status flag Input capture error flag Others Miscellaneous register System clock select register bits 2,1 Bank register
Abbr. (TWBU, TWBL) (TWCU, TWCL) (TWDU, TWDL) (OC) (AMR) (ADRL, ADRU) (LCR) (LMR) (LOR1) (LOR2) (LOR3) (LSON) (WDON) (ADSF) (DTON) (ICSF) (ICEF) (MIS) (SSR2, SSR1) (V)
Contents -- -- -- -- Refer to description of A/D mode register Refer to description of A/D data register Refer to description of LCD control register Refer to description of LCD duty-cycle/clock control register Sets R-port/LCD segment pins to R port mode
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. - indicates that the bit does not exist.
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HD404829R Series
Status After Cancellation of Stop Mode by STOPC Input Status After Cancellation of Stop Mode by RESET Input Status After all Other Types of Reset Pre-MCU-reset values are not guaranteed; values must be initialized by program
Item Carry flag Accumulator B register W register X/SPX register Y/SPY register Serial data register RAM RAM enable flag Port mode register C bit 2 System clock select register bit 3
Abbr. (CA) (A) (B) (W) (X/SPX) (Y/SPY) (SRL, SRU)
Pre-stop-mode values are not guaranteed; values must be initialized by program
Pre-stop-mode values are retained (RAME) (PMRC2) (SSR3) 1 Pre-stop-mode values are retained 0 0 0 0
Interrupts The MCU has 11 interrupt sources: five external signals (INT0, INT1, INT 2-INT 4), four timer/ counters (timers A, B, C, and D), serial interface, and A/D converter. An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. Some vector addresses are shared by two different interrupts. They are timer B and INT2, timer C and INT 3, timer D and INT4, and A/D converter and serial interface interrupts. So the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
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HD404829R Series
during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program.
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt RESET, STOPC* INT0 INT1 Timer A Timer B, INT2 Timer C, INT3 Timer D, INT4 A/D, Serial Priority -- 1 2 3 4 5 6 7 Vector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E
Note: * The STOPC interrupt request is valid only in stop mode.
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HD404829R Series
$ 000,0 IE $ 000,2 IFO $ 000,3 IMO Priority controller INT1 interrupt $ 001,0 IF1 $ 001,1 IM1 $ 001,2 IFTA $ 001,3 IMTA Timer B interrupt $ 002,0 IFTB $ 002,1 IMTB Timer C interrupt $ 002,2 IFTC $ 002,3 IMTC Timer D interrupt $ 003,0 IFTD $ 003,1 IMTD A/D interrupt $ 003,2 IFAD $ 003,3 IMAD Note: $m,n is RAM address $m, bit number n. $ 022,0 IF2 INT2 interrupt $ 022,1 IM2 $ 022,2 IF3 INT3 interrupt $ 022,3 IM3 $ 023,0 IF4 INT4 interrupt $ 023,1 IM4 $ 023,2 Serial interrupt IFS $ 023,3 IMS Vector address Interrupt request
INT0 interrupt
Timer A interrupt
Figure 9 Interrupt Control Circuit
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HD404829R Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source Interrupt Cuntrol Bit IE IF0 . IM0 IF1 . IM1 IFTA . IMTA IFTB . + IF2 . IFTC . + IF3 . IMTB IM2 IMTC IM3 INT0 1 1 * * * * * * INT1 1 0 1 * * * * * Timer A 1 0 0 1 * * * * Timer B or INT2 1 0 0 0 1 * * * Timer C or INT3 1 0 0 0 0 1 * * Timer D or INT4 1 0 0 0 0 0 1 * A/D or Serial 1 0 0 0 0 0 0 1
IFTD . IMTD + IF4 . IM4 IFAD . IMAD + IFS . IMS
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles 1 2 3 4 5 6
Instruction execution*
Interrupt acceptance
Stacking IE reset Vector address generation
Execution of JMPL instruction at vector address
Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction.
Execution of instruction at start address of interrupt routine
Figure 10 Interrupt Processing Sequence
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HD404829R Series
Power on
RESET = 1? Yes
No
Interrupt request? No
Yes
No
IE = 1? Yes
Reset MCU
Execute instruction
Accept the interrupt
PC (PC) + 1
IE 0 Stack (PC) Stack (CA) Stack (ST)
PC $0002
Yes
INT0 interrupt? No
PC $0004
Yes
INT1 interrupt? No
PC $0006
Yes
Timer-A interrupt? No
PC $0008
Yes
Timer-B/INT2 interrupt? No
PC $000A
Yes
Timer-C/INT3 interrupt? No
PC $000C
Yes
Timer-D/INT4 interrupt? No
PC $000E
(A/D, serial interrupt)
Figure 11 Interrupt Processing Flowchart
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HD404829R Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE 0 1 Interrupt Enabled/Disabled Disabled Enabled
External Interrupts (INT0, INT1, INT2-INT4): Five external interrupt signals. External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2-IF4 are set at the rising or falling edge of signals input to INT 2-INT 4, as listed in table 5. The INT2-INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Table 5 External Interrupt Request Flags (IF0-IF4: $000, $001, $022, $023)
IF0-IF4 0 1 Interrupt Request No Yes
Detection edge selection register 1 (ESR1: $026) Bit Initial value Read/Write Bit name 3 0 W ESR13 2 0 W ESR12 1 0 W ESR11 0 0 W ESR10
ESR13 0
ESR12 0 1
INT3 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
ESR11 0
ESR10 0 1
INT2 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 12 Detection Edge Selection Register 1 (ESR1)
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HD404829R Series
Detection edge selection register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection *
ESR21 0
ESR20 0 1
INT4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 13 Detection Edge Selection Register 2 (ESR2)
External Interrupt Masks (IM0-IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0-IM4: $000, $001, $022, $023)
IM0-IM4 0 1 Interrupt Request Enabled Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA-IFTD 0 1 Interrupt Request No Yes
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HD404829R Series
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA-IMTD 0 1 Interrupt Request Enabled Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 7.
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 8.
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 7.
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 8.
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table 7.
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 8.
Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 9. Table 9 Serial Interrupt Request Flag (IFS: $023, Bit 2)
IFS 0 1 Interrupt Request No Yes
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HD404829R Series
Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 10. Table 10 Serial Interrupt Mask (IMS: $023, Bit 3)
IMS 0 1 Interrupt Request Enabled Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in table 11. Table 11 A/D Interrupt Request Flag (IFAD: $003, Bit 2)
IFAD 0 1 Interrupt Request No Yes
A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 12. Table 12 A/D Interrupt Mask (IMAD: $003, Bit 3)
IMAD 0 1 Interrupt Request Enabled Disabled (masked)
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HD404829R Series
Operating Modes
The MCU has five operating modes as shown in table 13. The operations in each mode are listed in tables 14 and 15. Transitions between operating modes are shown in figure 14. Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Table 13 Operating Modes and Clock Status
Mode Name Active Activation method RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) System oscillator Subsystem oscillator Cancellation method Operating Standby SBY instruction from active mode Stop STOP instruction when TMA3 = 0 Watch STOP instruction when TMA3 = 1 or SBY instruction from subactive mode (when LSON = 1, or LSON and DTON are both 0) Subactive*2 AN interrupt request from timer A or INT0 in watch mode when LSON = 1
Status
Operating
Stopped
Stopped
Stopped
Operating *1 RESET input, STOP/SBY instruction
Operating *1
Operating *1
Operating *1 RESET input, INT0 or timer A interrupt request
Operating *1 RESET input, STOP/SBY instruction
RESET input, RESET input, interrupt STOPC input request in stop mode
Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list.
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HD404829R Series
Table 14 Operations in Low-Power Dissipation Modes
Function CPU RAM Timer A Timer B Timer C Timer D Serial interface A/D LCD I/O Notes: 1. 2. 3. 4. Stop Mode Reset Retained Reset Reset Reset Reset Reset Reset Reset Reset *1 Watch Mode Retained Retained Operating Stopped Stopped Stopped Stopped *3 Stopped Operating Retained
*4
Standby Mode Retained Retained Operating Operating Operating Operating Operating Operating Operating Retained
Subactive Mode*2 Operating Operating Operating Operating Operating Operating Operating Stopped Operating Operating
Output pins are at high impedance. Subactive mode is an optional function specified on the function option list. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. When a 32-kHz clock source is used.
Table 15 I/O Status in Low-Power Dissipation Modes
Output Standby Mode, Watch Mode D0-D 9 D10-D 11 R0-R7 Retained -- Retained or output of peripheral functions Stop Mode High impedance -- High impedance Input Active Mode, Subactive Mode Input enabled Input enabled Input enabled
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HD404829R Series
Reset by RESET input or by watchdog timer
Stop mode
(TMA3 = 0, SSR3 = 0)
RAME = 0 RESET1
RAME = 1 RESET2
STOPC
STOPC
Active mode STOP fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate Stop fcyc fcyc SBY Interrupt fOSC: fX: o CPU : o CLK : o PER : Oscillate Oscillate fcyc fcyc fcyc
(TMA3 = 0)
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop Stop Stop
Standby mode
(TMA3 = 0, SSR3 = 1)
STOP
fOSC: fX: o CPU : o CLK : o PER :
Stop Stop Stop Stop Stop
Watch mode
(TMA3 = 1) (TMA3 = 1, LSON = 0)
fOSC: fX: o CPU : o CLK : o PER :
Oscillate Oscillate Stop fW fcyc
SBY Interrupt
fOSC: fX: o CPU : o CLK : o PER :
Oscillate Oscillate fcyc fW fcyc
STOP INT0, timer A*1
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop fW Stop
*3
Main oscillation frequency Suboscillation frequency for time-base fOSC/4 fcyc: fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 o CPU : CPU operating clock o CLK : Timer A operating clock o PER : Clock for peripheral functions (except timer A) LSON: Low speed on flag DTON: Direct transfer on flag
fOSC: fX:
*2
Subactive mode fOSC: fX: o CPU : o CLK : o PER : Stop Oscillate fSUB fW fSUB
*4
STOP
(TMA3 = 1, LSON = 1)
INT0, timer A*1
fOSC: fX: o CPU : o CLK : o PER :
Stop Oscillate Stop fW Stop
Notes: 1. 2. 3. 4.
Interrupt source STOP/SBY (DTON = 1, LSON = 0) STOP/SBY (DTON = 0, LSON = 0) STOP/SBY (DTON = Don't care, LSON = 1)
Figure 14 MCU Status Transitions
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HD404829R Series
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 15.
Stop mode
Standby mode
Watch mode
No
RESET = 1?
RESET = 1?
No
Yes No
STOPC = 0?
Yes
IF0 * IM0 = 1?
No
Yes
IF1 * IM1 = 1?
No
Yes Yes
*1 IFTA * IMTA = 1?
No
IFTB * IMTB + IF2 * IM2 = 1?
RAME = 1
Yes
RAME = 0
No
IFTC * IMTC + IF3 * IM3 = 1?
Yes
*1
No
IFTD * IMTD + IF4 * IM4 = 1?
Yes *1
No
Yes*1
*2
No Yes*1
System clock oscillator started Next instruction execution System reset
No IF = 1, IM = 0, IE = 1? Yes
System clock oscillator started
Notes: 1. Only when clearing from standby mode 2. IFAD * IMAD + IFS * IMS = 1
Next instruction execution
Interrupts enabled
Figure 15 MCU Operation Flowchart
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HD404829R Series
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register (SSR: $029; operating: SSR3 = 0, stop: SSR3 = 1) (figure 27). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 44). Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.
Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution (at least equal to oscillator stabilization time tRC)
Figure 16 Timing of Stop Mode Cancellation
Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD function operate, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive mode.
Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC ) for an INT 0 interrupt, as shown in figures 17 and 18. Operation during mode transition is the same as that at standby mode cancellation (figure 15).
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HD404829R Series
Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because the operating clock is slow, the power dissipation becomes low, next to watch mode. The CPU instruction execution speed can be selected as 244 s or 122 s by setting bit 2 (SSR2) of the system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, CLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/ INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing.
Oscillation stabilization period Active mode Watch mode Active mode
Interrupt strobe INT0 Interrupt request generation tRC
(During the transition from watch mode to active mode only) T: Interrupt frame length t RC : Oscillation stabilization period
T
T TX
Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered and is designated Tx, then Tx will be in the following range: T + tRC Tx 2T + tRC
Figure 17 Interrupt Frame
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HD404829R Series
Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: * Set LSON to 0 and DTON to 1 in subactive mode. * Execute the STOP or SBY instruction. * The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19).
Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name MIS3 3 0 W MIS3 MIS2 2 0 W MIS2 MIS1 0 1 0 W MIS1 MIS0 0 0 0 W MIS0 T*1 tRC * 1 Oscillation circuit conditions External clock input
Buffer control. Refer to figure 41.
0.24414 ms 0.12207 ms 0.24414 ms* 2
0 1 1
1 0 1
15.625 ms 7.8125 ms 62.5 ms Not used 31.25 ms Not used
Ceramic oscillator Crystal oscillator --
Notes: 1. Values of T and tRC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. 2. The value is applied only when direct transfer operation is used.
Figure 18 Miscellaneous Register (MIS)
STOP/SBY instruction execution Subactive mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T TD Interrupt frame length T: t RC : Oscillation stabilization period TD : Direct transition time t RC MCU internal processing time Oscillation stabilization time
Active mode
Figure 19 Direct Transition Timing
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HD404829R Series
Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program. MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by an asynchronous RESET input, regardless of its status. The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 1 ? Yes RAME = 0
No
MCU operation cycle
Reset MCU
Figure 20 MCU Operating Sequence (Power On)
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HD404829R Series
MCU operation cycle
IF = 1?
Yes
No
No
IM = 0 and IE = 1?
Instruction execution
Yes
Yes
SBY/STOP instruction?
IE 0 Stack (PC), (CA), (ST)
No
Low-power mode operation cycle
PC Next location
PC Vector address
IF: IM: IE: PC: CA: ST:
Interrupt request flag Interrupt mask Interrupt enable flag Program counter Carry flag Status flag
Figure 21 MCU Operating Sequence (MCU Operation Cycle)
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HD404829R Series
STOP/SBY Instruction
IF = 1 and IM = 0?
No
Yes
Standby/watch mode
Stop mode
No
IE = 0
*
No Interrupt service routine Yes
IF = 1 and IM = 0?
No
STOPC = 0?
Yes Hardware NOP execution Hardware NOP execution
Yes
RAME = 1
PC (PC)+1
PC (PC)+1
Reset MCU
Instruction execution
MCU operation cycle Note: *Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation.
Figure 22 MCU Operating Sequence (Low-Power Mode Operation)
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HD404829R Series
Notes: 1. When watch mode or subactive mode on HD404829R Series/HD4074829 is used and the LCD function is off in that mode, the watch mode or subactive mode current is larger, and consequently the following settings should be made. Perform the following writes in the order shown before the transition to watch mode (before execution of the STOP instruction): Write $0 to LCR Write $3 to LMR Also, when returning to active mode from watch mode or subactive mode, perform the following writes in the order shown: Write a value appropriate to the conditions of use to LMR Write a value appropriate to the conditions of use to LCR A sample programming flowchart for the above procedures is shown in figure 23.
. . . LMR LCR . . .
Set appropriate values for active mode
Initialization routine
. . . LCR = $0 LMR. = $3 . .
Include these operations
Main routine
STOP instruction Watch mode Or transition to subactive mode
After the MCU enters active mode again . . . LMR LCR . . . Set appropriate values for active mode INT 0 or timer A interrupt processing routine
Figure 23 Programming Flowchart (LCD Display Off in Watch or Subactive Mode)
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HD404829R Series
Notes: 2. When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 24. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. In figure 25, the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame.
INT0
Sampling High Low Low
Figure 24 Edge Detection
INT0
INT0
Interrupt frame
A: Low
B: Low
Interrupt frame
A: High
B: High
(a) High level period
(b) Low level period
Figure 25 Sampling Example
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HD404829R Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 26. As shown in table 16, a ceramic oscillator can be connected to OSC 1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock select register (SSR: $029) must be set according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 27). Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency, DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.
LSON
OSC2 OSC1
1/4 System fOSC division clock circuit oscillator
fcyc tcyc
Timing generation circuit
oCPU System clock selection circuit oPER
CPU with ROM, RAM, registers, flags, and I/O
fX
X1 X2
Subsystem clock oscillator
fSUB 1/8 or 1/4 Timing division tsubcyc generation circuit * circuit TMA3 bit
Internal peripheral module interrupt (other than timer A)
1/8 division circuit
fW tWcyc
Timing generation circuit
Clock Time-base oCLK clock selection circuit
Time A interrupt
Note: * 1/8 or 1/4 division ratio can be selected by setting bit 2 of the system clock select register (SSR: $029).
Figure 26 Clock Generation Circuit
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HD404829R Series
System clock select register (SSR: $029) Bit Initial value Read/Write Bit name SSR3 0 1 3 0 W SSR3 2 0 W SSR2 1 -- -- -- 0 -- -- -- SSR1 0 1 System clock selection fOSC = 400 kHz to 1 MHz fOSC = 1.6 to 4.2 MHz
32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode 32-kHz oscillation division ratio selection fSUB = fX/8 fSUB = fX/4
SSR2 0 1
Note: SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input duringstop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode.
Figure 27 System Clock Select Register (SSR)
D0 GND X2 X1 RESET OSC2 OSC1 TEST GND AVSS
Figure 28 Typical Layouts of Crystal and Ceramic Oscillator
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HD404829R Series
Table 16 Oscillator Circuit Examples
Circuit Configuration External clock operation
External oscillator OSC 1
Circuit Constants --
Open
OSC 2
Ceramic oscillator (OSC1, OSC 2)
Ceramic oscillator: CSB400P22 (Murata) CSB400P (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5%
C1 OSC1 Ceramic oscillator Rf OSC2 C2 GND
Ceramic oscillator: CSB800J122 (Murata) CSB800J (Murata) Rf = 1 M 20% C1 = C2 = 220 pF 5% Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20% Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M 20% C1 = C2 = 30 pF 20%
Crystal oscillator (OSC1, OSC 2)
C1 Crystal oscillator Rf OSC1
Rf = 1 M 20% C1 = C2 = 10 to 22pF 20% Crystal : Equivalent circuit at left C0 =7pF max Rs = 100 max
OSC2 C2 GND
OSC1
L
CS C0
RS
OSC2
Crystal oscillator (X1, X2)
C1 X1 Crystal oscillator X2 C2 GND L X1 C0 CS RS X2
Crystal oscillator: 32.768 kHz: MX38T (Nippon Denpa) C1 = C2 = 20 pF 20% RS: 14 k C0: 1.5 pF
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HD404829R Series
Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1, OSC 2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 28. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open.
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HD404829R Series
Input/Output
The MCU has 42 input/output pins (D 0-D 9, R0 0-R7 3 ) and 2 input pins (D10 , D11 ). The features are described below. * Ten pins (D0-D9) are high-current input/output pins. * The D10 and D11, and R0 0-R7 3 input/output pins are multiplexed with peripheral function pins such as for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output selection are automatically switched according to the setting. * Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. * Peripheral function output pins are CMOS output pins. Only the R23/SO pin can be set to NMOS opendrain output by software. * In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output pins are in high-impedance state. * Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by software. I/O buffer configuration is shown in figure 29, programmable I/O circuits are listed in table 17, and I/O pin circuit types are shown in table 18. Table 17 Programmable I/O Circuits
MIS3 (bit 3 of MIS) DCD, DCR PDR CMOS buffer PMOS NMOS Pull-up MOS Note: -- indicates off status. 0 -- -- -- 0 1 -- -- -- 0 -- On -- 0 1 1 On -- -- 0 -- -- -- 0 1 -- -- On 0 -- On -- 1 1 1 On -- On
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HD404829R Series
HLT VCC VCC Pull-up MOS Buffer control signal DCD, DCR Pull-up control signal MIS3
Output data
PDR
Input data Input control signal
Figure 29 I/O Buffer Configuration Table 18 Circuit Configurations of I/O Pins
I/O Pin Type Input/output pins Circuit
VCC HLT VCC Pull-up control signal Buffer control signal Output data Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal MIS3 DCR MIS2 PDR MIS3 DCD, DCR PDR
Pins D0 - D9 R0 0-R0 3 R1 0-R1 3 R2 0-R2 2 R3 0-R3 3 R4 0-R4 3 R5 0-R5 3 R6 0-R6 3 R7 0-R7 3 R2 3
Output data Input data Input control signal
Input pins
Input data Input control signal
D10, D11
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HD404829R Series
Table 18 Circuit Configurations of I/O Pins (cont)
I/O Pin Type Peripheral function pins Input/output pins Circuit
VCC HLT VCC Pull-up control signal MIS3
Pins SCK
Output data Input data SCK
SCK
Output pins
VCC
HLT VCC Pull-up control signal MIS3
SO
PMOS control signal Output data
VCC
MIS2 SO
HLT VCC Pull-up control signal MIS3
TOB, TOC, TOD
Output data
TOB, TOC, TOD
Input pins
VCC
HLT MIS3 PDR Input data Input data SI, INT1, etc INT0, STOPC
SI, INT1, INT2, INT3, INT4, EVNB, EVND
INT0, STOPC
Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal becomes low, and input/output pins enter high-impedance state. 2. The HLT signal is 1 in watch and subactive modes.
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HD404829R Series
D Port (D0-D11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0-D9 are highcurrent I/O pins, and D10 and D11 are input-only pins. Pins D 0-D 9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions. Output data is stored in the port data register (PDR) for each pin. All pins D0-D11 are tested by the TD and TDD instructions. The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0-DCD2: $02C-$02E) that are mapped to memory addresses (figure 30). Pins D10 and D 11 are multiplexed with peripheral function pins STOPC and INT0, respectively. The peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode register C (PMRC: $025) (figure 31). R Ports (R0 0-R73): 32 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled by R-port data control registers (DCR0-DCR7: $030-$037) that are mapped to memory addresses (figure 30). Pins R00-R03 are multiplexed with peripheral pins INT1-INT 4, respectively. The peripheral function modes of these pins are selected by bits 0-3 (PMRB0-PMRB3) of port mode register B (PMRB: $024) (figure 32). Pins R10-R12 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2 (TMB2: $013), bits 0-2 (TMC20-TMC22) of timer mode register C2 (TMC2: $014), and bits 0-3 (TMD20-TMD23) of timer mode register D2 (TMD2: $015) (figures 33, 34, and 35). Pins R13 and R20 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C (PMRC: $025) (figure 31). Pins R21-R23 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 36 and 37. Ports R3 and R4 are multiplexed with segment pins SEG1-SEG8, respectively. The function modes of these pins can be selected by individual pins, by setting LCD output registers 1 and 2 (LOR1, LOR2: $01D, $01F) (figures 38 and 39). Ports R5-R7 are multiplexed with segment pins SEG9-SEG20, respectively. The function modes of these pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 40).
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HD404829R Series
Data control register DCD0, DCD1 Bit Initial value Read/Write Bit name DCD2 Bit Initial value Read/Write Bit name (DCD0 to 2: $02C to $02E) (DCR0 to 7: $030 to $037) 2 0 W 1 0 W 0 0 W
3 0 W
DCD03, DCD02, DCD01, DCD00, DCD13 DCD12 DCD11 DCD10 3 -- -- 2 -- -- 1 0 W 0 0 W DCD20
Not used Not used DCD21
DCR0 to DCR7 Bit Initial value Read/Write Bit name
3 0 W
2 0 W
1 0 W
0 0 W
DCR03- DCR02- DCR01- DCR00- DCR73 DCR72 DCR71 DCR70 CMOS Buffer On/Off Selection Off (high-impedance) On
All Bits 0 1
Correspondence between ports and DCD/DCR bits Register Name DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR5 DCR6 DCR7 Bit 3 D3 D7 -- R03 R13 R23 R33 R43 R53 R63 R73 Bit 2 D2 D6 -- R02 R12 R22 R32 R42 R52 R62 R72 Bit 1 D1 D5 D9 R01 R11 R21 R31 R41 R51 R61 R71 Bit 0 D0 D4 D8 R00 R10 R20 R30 R40 R50 R60 R70
Figure 30 Data Control Registers (DCD, DCR)
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HD404829R Series
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name PMRC3 0 1 PMRC2 0 1 3 0 W PMRC3 2 0 W 1 0 W 0 0 W PMRC0 PMRC0 0 1 PMRC1 0 1 R13/EVNB mode selection R13 EVNB R20/EVND mode selection R20 EVND
PMRC2 * PMRC1
D11/INT0 mode selection D11 INT0 D10/STOPC mode selection D10 STOPC
Note: * PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRC2 is not reset but retains its value.
Figure 31 Port Mode Register C (PMRC)
Port mode register B (PMRB: $024) Bit Initial value Read/Write Bit name PMRB3 0 1 PMRB2 0 1 3 0 W PMRB3 2 0 W 1 0 W 0 0 W
PMRB2 PMRB1 PMRB0 PMRB0 0 1 PMRB1 0 1 R00/INT1 mode selection R00 INT1 R01/INT2 mode selection R01 INT2
R03/INT4 mode selection R03 INT4 R02/INT3 mode selection R02 INT3
Figure 32 Port Mode Register B (PMRB)
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HD404829R Series
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20
Not used Not used TMB21
TMB21 0
TMB20 0 1
R10/TOB mode selection R10 TOB TOB TOB R10 port Toggle output 0 output 1 output
1
0 1
Figure 33 Timer Mode Register B2 (TMB2)
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name TMC22 0 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22 TMC21 0 TMC20 0 1 1 0 1
R11/TOC mode selection R11 TOC TOC TOC -- R11 port Toggle output 0 output 1 output Not used
1
0
0 1
1
0 1 TOC PWM output
Figure 34 Timer Mode Register C2 (TMC2)
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HD404829R Series
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name TMD23 0 3 0 R/W TMD23 TMD22 0 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD21 0
TMD20 0 1
R12/TOD mode selection R12 TOD TOD TOD -- R12 port Toggle output 0 output 1 output Not used
1
0 1
1
0
0 1
1
0 1 TOD R12 PWM output Input capture (R12 port)
1
!
!
!
! : Don't care
Figure 35 Timer Mode Register D2 (TMD2)
Serial mode register A (SMRA: $005) Bit Initial value Read/Write Bit name 3 0 W SMRA3 2 0 W 1 0 W 0 0 W SMRA0 Prescaler division ratio /2048 /512 /128 /32 /8 /2 -- --
SMRA2 SMRA1
SMRA3 0 1
R21/SCK mode selection R21 SCK
SMRA2 SMRA1 SMRA0 0 0 0 1 1 0 1 1 0 0 1 1 0 1
SCK Output Output Output Output Output Output Output Input
Clock source Prescaler Prescaler Prescaler Prescaler Prescaler Prescaler System clock External clock
Figure 36 Serial Mode Register A (SMRA)
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HD404829R Series
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name PMRA1 0 1 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0 R22/SI mode selection R22 SI PMRA0 0 1 R23/SO mode selection R23 SO
Figure 37 Port Mode Register A (PMRA)
LCD output register 1 (LOR1: $01D) Bit Initial value Read/Write Bit name LOR13 0 1 LOR12 0 1 3 0 W LOR13 2 0 W LOR12 1 0 W LOR11 0 0 W LOR10 R31/SEG2 mode selection R31 SEG2 R30/SEG1 mode selection R30 SEG1
R33/SEG4 mode selection R33 SEG4 R32/SEG3 mode selection R32 SEG3
LOR11 0 1 LOR10 0 1
Figure 38 LCD Output Register 1 (LOR1)
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HD404829R Series
LCD output register 2 (LOR2: $01E) Bit Initial value Read/Write Bit name LOR23 0 1 LOR22 0 1 3 0 W LOR23 2 0 W LOR22 1 0 W LOR21 0 0 W LOR20 R41/SEG6 mode selection R41 SEG6 R40/SEG5 mode selection R40 SEG5
R43/SEG8 mode selection R43 SEG8 R42/SEG7 mode selection R42 SEG7
LOR21 0 1 LOR20 0 1
Figure 39 LCD Output Register 2 (LAOR2)
LCD output register 3 (LOR3: $01F) Bit Initial value Read/Write Bit name LOR32 0 1 3 -- -- 2 0 W 1 0 W LOR31 0 0 W LOR30 LOR31 0 1 LOR30 0 1 R60/SEG13-R63/SEG16 mode selection R60-R63 SEG13-SEG16 R50/SEG9-R53/SEG12 mode selection R50-R53 SEG9-SEG12
Not used LOR32
R70/SEG17-R73/SEG20 mode selection R70-R73 SEG17-SEG20
Figure 40 LCD Output Register 3 (LOR3)
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HD404829R Series
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each input/output pin other than input-only pins D10 and D 11 . The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin--enabling on/off control of that pin alone (table 17 and figure 41). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0 CMOS buffer on/off selection for pin R23 /SO On Off
MIS3 0 1
Pull-up MOS on/off selection Off On
MIS2 0 1
MIS1
MIS0
tRC selection. Refer to figure 18 in the operation modes section.
Figure 41 Miscellaneous Register (MIS)
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HD404829R Series
Prescalers
The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 19, and the prescalers output supply is shown in figure 42. The timers A-D input clocks except external events, the serial transmit clock except the external clock, and the LCD circuit operating clock are selected from the prescaler outputs, depending on corresponding mode registers. Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. Table 19 Prescaler Operating Conditions
Prescaler Prescaler S Input Clock System clock (in active and standby mode), Subsystem clock (in subactive mode) 32-kHz crystal oscillation Reset Conditions MCU reset Stop Conditions MCU reset, stop mode, watch mode MCU reset, stop mode
Prescaler W
MCU reset, software
LCD Subsystem clock Prescaler W Timer A Timer B Timer C System clock Clock selector Prescaler S Timer D Serial
Figure 42 Prescaler Output Supply
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HD404829R Series
Timers
The MCU has four timer/counters (A to D). * * * * Timer A: Timer B: Timer C: Timer D: Free-running timer Multifunction timer Multifunction timer Multifunction timer
Timer A is an 8-bit free-running timer. Timers B-D are 8-bit multifunction timers, whose functions are listed in table 20. The operating modes are selected by software. Table 20 Timer Functions
Functions Clock source Prescaler S Prescaler W External event Timer functions Free-running Time-base Event counter Reload Watchdog Input capture Timer outputs Toggle 0 output 1 output PWM Note: -- implies not available. Timer A Available Available -- Available Available -- -- -- -- -- -- -- -- Timer B Available -- Available Available -- Available Available -- -- Available Available Available -- Timer C Available -- -- Available -- -- Available Available -- Available Available Available Available Timer D Available -- Available Available -- Available Available -- Available Available Available Available Available
Timer A Timer A Functions: Timer A has the following functions. * Free-running timer * Clock time-base The block diagram of timer A is shown in figure 43.
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HD404829R Series
32.768-kHz oscillator 1/4 1/2 2 fW 1/2 twcyc Selector Internal data bus 59 Selector Clock Timer counter A (TCA) Overflow fW twcyc Prescaler W (PSW)
/2 /8 / 16 / 32
Timer A interrupt request flag (IFTA)
Selector
/2 /4 /8 / 32 / 128 / 512 / 1024 / 2048
System clock
o PER
Prescaler S (PSS)
3 Timer mode register A (TMA)
Data bus Clock line Signal line
Figure 43 Block Diagram of Timer A Timer A Operations: * Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA: $008). * Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied to timer A after it has reached * $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore it generates regular interrupts every 256 clocks. * Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and timer A can be reset to $00 by software. Registers for Timer A Operation: Timer A operating modes are set by the following registers. * Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 44.
HD404829R Series
Timer mode register A (TMA: $008) Bit Initial value Read/Write Bit name 3 0 W TMA3 2 0 W TMA2 1 0 W TMA1 0 0 W TMA0
Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 ! : Don't care ! PSS PSS PSS PSS PSS PSS PSS PSS PSW PSW PSW PSW -- -- -- 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc 32tWcyc 16tWcyc 8tWcyc 2tWcyc 1/2tWcyc Not used Reset PSW and TCA
Operating mode Timer A mode
Time-base mode
Note: 1. tWcyc = 244.14 s (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) x 256. 3. If PSW of TCA reset is selected while the LCD is operating, LCD operation halts (power switch goes off and all SEG and COM pins are grounded). When an LCD is connected for display, the PSW and TCA reset periods must be set in the program to the minimum. 4. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur.
Figure 44 Timer Mode Register A (TMA)
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HD404829R Series
Timer B Timer B Functions: Timer B has the following functions. * Free-running/reload timer * External event counter * Timer output operation (toggle, 0, and 1 outputs) The block diagram of timer B is shown in figure 45.
Timer B ineterrupt request flag (IFTB) TOB Timer output control logic
EVNB
Timer read register BL (TRBL) /2 /4 Prescaler S (PSS) /8 /32 /128 /512 /2048 4 Selector
Timer read register BU (TRBU)
Overflow
System clock
Free-runnning/Reload control
PER
(TCBL) 4
(TCBU) 4
Timer counter B (TWBL) (TWBU)
3
Timer mode register B1 (TMB1) 2 Edge detection control
Timer mode register B2 (TMB2)
Data bus Clock line Signal line
Figure 45 Block Diagram of Timer B
Internal data bus
Timer counter B
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HD404829R Series
Timer B Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register B1 (TMB1: $009). Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by software and incremented by one at each clock input. If an input clock is applied to timer B after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is initialized to its initial value set in timer write register B; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer B is used as an external event counter by selecting external event input as input clock source. In this case, pin R13/EVNB must be set to EVNB by port mode register C (PMRC: $025). Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following three output modes can be selected for timer B by setting timer mode register B2 (TMB2: $013). Toggle 0 output 1 output By selecting the timer output mode, pin R10/TOB is set to TOB. The output from TOB is reset low by MCU reset. Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input after timer B has reached $FF. By using this function and reload timer function, clock signals can be output at a required frequency for the buzzer. The output waveform is shown in figure 46. 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is high. 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B has reached $FF. Note that this function must be used only when the output level is low.
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HD404829R Series
Toggle output waveform (timers B, C, and D) Free-running timer
256 clock cycles Reload timer
256 clock cycles
(256 - N) clock cycles (256 - N) clock cycles
PWM output waveform (timers C and D) T x (N + 1)
TMC13 = 0 TMD13 = 0 T x 256
T TMC13 = 1 TMD13 = 1
T x (256 - N) Note: The waveform is always fixed low when N = $FF. T: Input clock period to counter (figures 52 and 60) N: The value of the timer write register
Figure 46 Timer Output Waveform
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HD404829R Series
Registers for Timer B Operation: By using the following registers, timer B operation modes are selected and the timer B count is read and written. Timer mode register B1 (TMB1: $009) Timer mode register B2 (TMB2: $013) Timer write register B (TWBL: $00A, TWBU: $00B) Timer read register B (TRBL: $00A, TRBU: $00B) Port mode register C (PMRC: $025) * Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 47. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register B1 write instruction. Setting timer B's initialization by writing to timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
Timer mode register B1 (TMB1: $009) Bit Initial value Read/Write Bit name 3 0 W TMB13 2 0 W TMB12 1 0 W TMB11 0 0 W TMB10 Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R13/EVNB (external event input)
TMB13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMB12 0
TMB11 0
TMB10 0 1
1
0 1
1
0
0 1
1
0 1
Figure 47 Timer Mode Register B1 (TMB1)
Timer mode register B2 (TMB2: $013) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 R/W 0 0 R/W TMB20 1 TMB21 0 TMB20 0 1 0 1 R10/TOB mode selection R10 TOB TOB TOB R10 port Toggle output 0 output 1 output
Not used Not used TMB21
Figure 48 Timer Mode Register B2 (TMB2)
64
HD404829R Series
* Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode as shown in figure 48. It is reset to $0 by MCU reset. * Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit (TWBL) and the upper digit (TWBU) as shown in figures 49 and 50. The lower digit is reset to $0 by MCU reset, but the upper digit value is invalid. Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the timer B value. Timer B is initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value needs no change, writing only to the upper digit initializes timer B.
Timer write register B (lower digit) (TWBL: $00A) Bit Initial value Read/Write Bit name 3 0 W TWBL3 2 0 W TWBL2 1 0 W TWBL1 0 0 W TWBL0
Figure 49 Timer Write Register B Lower Digit (TWBL)
Timer write register B (upper digit) (TWBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWBU3 W TWBU2 W TWBU1 W TWBU0
Figure 50 Timer Write Register B Upper Digit (TWBU) * Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit (TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 51 and 52). The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading TRBL, the count of timer B when TRBU is read can be obtained.
65
HD404829R Series
Timer read register B (lower digit) (TRBL: $00A) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBL3 R TRBL2 R TRBL1 R TRBL0
Figure 51 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRBU3 R TRBU2 R TRBU1 R TRBU0
Figure 52 Timer Read Register B Upper Digit (TRBU) * Port mode register C (PMRC: $025): Write-only register that selects R13/EVNB pin function as shown in figure 53. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025) Bit Initial value Read/Write Bit name PMRC3 0 1 PMRC2 0 1 3 0 W PMRC3 2 0 W 1 0 W 0 0 W
PMRC2 PMRC1 PMRC0 PMRC1 0 1 PMRC0 0 1 R20/EVND mode selection R20 EVND R13/EVNB mode selection R13 EVNB
D11/INT0 mode selection D11 INT0 D10/STOPC mode selection D10 STOPC
Figure 53 Port Mode Register C (PMRC)
66
HD404829R Series
Timer C Timer C Functions: Timer C has the following functions. * Free-running/reload timer * Watchdog timer * Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 54.
67
HD404829R Series
System reset signal Watchdog on flag (WDON) TOC Timer output control logic Timer C interrupt request flag (IFTC)
Watchdog timer control logic
System clock
o PER Timer read register CL (TRCL) /2 /4 /8 Prescalers / 32 (PSS) / 128 / 512 / 1024 / 2048 Selector 4
Timer read register CU (TRCU)
(TCCL) Free-running/reload control 4
(TCCU) 4
Timer write register C (TWCL) (TWCU)
3 Timer mode register C1 (TMC1) 3
Timer output control Data bus Clock line Signal line
Timer mode register C2 (TMC2)
Figure 54 Block Diagram of Timer C
68
Internal data bus
Timer counter C
HD404829R Series
Timer C Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. * Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R11/TOC is set to TOC. The output from TOC is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output function. The output waveform differs depending on the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in figure 46.
69
HD404829R Series
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected and the timer C count is read and written. Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) * Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 55. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C1 (TMC1: $00D) Bit Initial value Read/Write Bit name TMC13 0 1 3 0 W TMC13 2 0 W TMC12 1 0 W TMC11 0 0 W TMC10 TMC12 0 TMC11 0 TMC10 0 1 1 0 1 1 0 0 1 1 0 1 Input clock period 2048tcyc 1024tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc
Free-running/reload timer selection Free-running timer Reload timer
Figure 55 Timer Mode Register C1 (TMC1)
70
HD404829R Series
* Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output mode as shown in figure 56. It is reset to $0 by MCU reset. * Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit (TWCL) and the upper digit (TWCU). The operation of timer write register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit (TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit. The operation of timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).
Timer mode register C2 (TMC2: $014) Bit Initial value Read/Write Bit name 3 -- -- 2 0 R/W 1 0 R/W TMC21 0 0 R/W TMC20
Not used TMC22
TMC22 0
TMC21 0
TMC20 0 1
R11/TOC mode selection R11 TOC TOC TOC -- R11 port Toggle output 0 output 1 output Not used
1
0 1
1
0
0 1
1
0 1 TOC PWM output
Figure 56 Timer Mode Register C2 (TMC2)
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HD404829R Series
Timer write register C (lower digit) (TWCL: $00E) Bit Initial value Read/Write Bit name 3 0 W TWCL3 2 0 W TWCL2 1 0 W TWCL1 0 0 W TWCL0
Figure 57 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWCU3 W TWCU2 W TWCU1 W TWCU0
Figure 58 Timer Write Register C Upper Digit (TWCU)
Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCL3 R TRCL2 R TRCL1 R TRCL0
Figure 59 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRCU3 R TRCU2 R TRCU1 R TRCU0
Figure 60 Timer Read Register C Upper Digit (TRCU)
72
HD404829R Series
Timer D Timer D Functions: Timer D has the following functions. * * * * Free-running/reload timer External event counter Timer output operation (toggle, 0, 1, and PWM outputs) Input capture timer
The block diagram for each operation mode of timer D is shown in figures 61 and 62. Timer D Operations: * Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D; if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or MCU reset. Refer to figure 3 and table 1 for details. * External event counter operation: Timer D is used as an external event counter by selecting the external event input as an input clock source. In this case, pin R20/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. * Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle 0 output 1 output PWM output By selecting the timer output mode, pin R12/TOD is set to TOD. The output from TOD is reset low by MCU reset. Toggle output: The operation is basically the same as that of timer-B's toggle output. 0 output: The operation is basically the same as that of timer-B's 0 output. 1 output: The operation is basically the same as that of timer-B's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output.
73
HD404829R Series
* Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R1 2/TOD is set to R1 2 and timer D is reset to $00.
74
HD404829R Series
Timer D interrupt request flag (IFTD) EVND Edge detection logic
System clock
oPER Timer read register DL (TRDL) /2 Prescaler S (PSS) /4 / 32 / 128 / 512 / 2048 /8 4
Timer read register DU (TRDU)
(TCDL) Free-running/reload control 4
(TCDU) 4
Timer write register D (TWDL) (TWDU)
3 Timer mode register D1 (TMD1) 2
Edge detection control
Edge detection selection register 2 (ESR2)
Data bus Clock line Signal line TOD Timer output control logic
Timer mode register D2 (TMD2) 3
Figure 61 Block Diagram of Timer D (Free-Running/Reload Timer)
Internal data bus
Timer counter D Selector
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HD404829R Series
Input capture status flag (ICSF) Input capture error flag (ICEF) Timer D interrupt request flag (IFTD)
Error control logic EVND Edge detection logic
Read signal
System clock
oPER Timer read register D (TRDL) /2 Prescaler S (PSS) /4 /32 /128 /512 /2048 Selector /8 Timer counter D (TCDL) (TCDU) Input capture timer control Overflow 4 (TRDU) 4 Internal data bus
3 Time mode register D1 (TMD1)
Timer mode register D2 (TMD2)
2
Edge detection control
Edge detection selection register 2 (ESR2)
Data bus Clock line Signal line
Figure 62 Block Diagram of Timer D (Input Capture Timer)
76
HD404829R Series
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) * Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 63. It is reset to $0 by MCU reset. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register D1 (TMD1: $010) Bit Initial value Read/Write Bit name 3 0 W TMD13 2 0 W TMD12 1 0 W TMD11 0 0 W TMD10 Input clock period and input clock source 2048tcyc 512tcyc 128tcyc 32tcyc 8tcyc 4tcyc 2tcyc R20/EVND (external event input)
TMD13 0 1
Free-running/reload timer selection Free-running timer Reload timer
TMD12 0
TMD11 0
TMD10 0 1
1
0 1
1
0
0 1
1
0 1
Figure 63 Timer Mode Register D1 (TMD1)
77
HD404829R Series
* Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output mode and input capture operation as shown in figure 64. It is reset to $0 by MCU reset. * Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit (TWDL) and the upper digit (TWDU). The operation of timer write register D is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B). * Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit (TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B). When the input capture timer operation is selected and if the count of timer D is read after a trigger is input, either the lower or upper digit can be read first. * Port mode register C (PMRC: $025): Write-only register that selects R20/EVND pin function as shown in figure 53. It is reset to $0 by MCU reset. * Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of signals input to pin EVND as shown in figure 69. It is reset to $0 by MCU reset.
Timer mode register D2 (TMD2: $015) Bit Initial value Read/Write Bit name 3 0 R/W TMD23 2 0 R/W TMD22 1 0 R/W TMD21 0 0 R/W TMD20
TMD23 0
TMD22 0
TMD21 0
TMD20 0 1
R12/TOD mode selection R12 TOD TOD TOD -- R12 port Toggle output 0 output 1 output Not used
1
0 1
1
0
0 1
1
0 1 TOD R12 PWM output Input capture (R12 port)
1
!
!
!
! : Don't care
Figure 64 Timer Mode Register D2 (TMD2)
78
HD404829R Series
Timer write register D (lower digit) (TWDL: $011) Bit Initial value Read/Write Bit name 3 0 W TWDL3 2 0 W TWDL2 1 0 W TWDL1 0 0 W TWDL0
Figure 65 Timer Write Register D Lower Digit (TWDL)
Timer write register D (upper digit) (TWDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined W TWDU3 W TWDU2 W TWDU1 W TWDU0
Figure 66 Timer Write Register D Upper Digit (TWDU)
Timer read register D (lower digit) (TRDL: $011) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDL3 R TRDL2 R TRDL1 R TRDL0
Figure 67 Timer Read Register D Lower Digit (TRDL)
Timer read register D (upper digit) (TRDU: $012) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R TRDU3 R TRDU2 R TRDU1 R TRDU0
Figure 68 Timer Read Register D Upper Digit (TRDU)
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HD404829R Series
Detection edge register 2 (ESR2: $027) Bit Initial value Read/Write Bit name 3 0 W ESR23 2 0 W ESR22 1 0 W ESR21 0 0 W ESR20
ESR23 0
ESR22 0 1
EVND detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
ESR21 0
ESR20 0 1
INT4 detection edge No detection Falling-edge detection Rising-edge detection Double-edge detection*
1
0 1
1
0 1
Note: * Both falling and rising edges are detected.
Figure 69 Detection Edge Select Register 2 (ESR2)
80
HD404829R Series
Note on Use When using the timer output as PWM output, note the following point. From the update of the timer write register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 21. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 21 PWM Output Following Update of Timer Write Register
PWM Output Mode Free running Timer Write Register is Updated during High PWM Output
Timer write register rewrite (set value is N)
Timer Write Register is Updated during Low PWM Output
Timer write register rewrite (set value is N)
Interrupt request generated
Interrupt request generated
T x (255 - N) T x (N + 1)
T x (N' + 1) T x (255 - N) T x (N + 1)
Reload
Timer write register rewrite (set value is N)
Interrupt request generated
Timer write register rewrite (set value is N)
Interrupt request generated
T
T x (255 - N)
T
T T x (255 - N) T
81
HD404829R Series
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features. * Multiple transmit clock sources External clock Internal prescaler output clock System clock * Output level control in idle states Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows. Serial data register (SRL: $006, SRU: $007) Serial mode register A (SMRA: $005) Serial mode register B (SMRB: $028) Miscellaneous register (MIS: $00C) Octal counter (OC) Selector The block diagram of the serial interface is shown in figure 70.
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HD404829R Series
Octal counter (OC) SO Idle controll logic Serial interrupt request flag (IFS)
SCK
I/O controll logic
Clock
Serial data register (SRL/U)
Internal data bus
SI oPER
Selector
System clock
Transfer control
1/2
Prescaler S (PSS)
/2 /8 /32 /128 /512 /2048
1/2
Selector
Serial mode register A (SMRA)
Serial mode register B (SMRB)
Data bus Clock line Signal line
Figure 70 Block Diagram of Serial Interface Serial Interface Operation Selecting and Changing the Operating Mode: table 22 lists the serial interface's operating modes. To select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface internally by writing data to serial mode register A. Note that the serial interface is initialized by writing data to serial mode register A. Refer to the following Serial Mode Register A section for details. Pin Setting: The R21/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The R2 2/SI and R23/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the following Registers for Serial Interface section for details. Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial Interface section for details. Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU: $007). Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the transmit clock and is input from or output to an external system. The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output level control in idle states is performed.
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HD404829R Series
Table 22 Serial Interface Operating Modes
SMRA Bit 3 1 Bit 1 0 PMRA Bit 0 0 1 1 0 1 Operating Mode Continuous clock output mode Transmit mode Receive mode Transmit/receive mode
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops. When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4tcyc to 8192tcyc by setting bits 2 to 0 (SMRA2- SMRA0) of serial mode register A (SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) as listed in table 23. Table 23 Serial Transmit Clock (Prescaler Output)
SMRB Bit 0 0 Bit 2 0 SMRA Bit 1 0 Bit 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 Prescaler Division Ratio / 2048 / 512 / 128 / 32 /8 /2 / 4096 / 1024 / 256 / 64 / 16 /4 Transmit Clock Frequency 4096t cyc 1024t cyc 256t cyc 64t cyc 16t cyc 4t cyc 8192t cyc 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc
Operating States: The serial interface has the following operating states; transitions between them are shown in figure 71. STS wait state Transmit clock wait state Transfer state Continuous clock output state (only in internal clock mode)
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HD404829R Series
* STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 71). In STS wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is then executed (01, 11), the serial interface enters transmit clock wait state. * Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However, note that if continuous clock output mode is selected in internal clock mode, the serial interface does not enter transfer state but enters continuous clock output state (17). The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04, 14) in transmit clock wait state. * Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is executed (05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In internal clock mode, the transmit clock stops after outputting eight clocks. In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial interface, and STS wait state is entered. If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set by the octal counter that is reset to 000. * Continuous clock output state (only in internal clock mode): Continuous clock output state is entered only in internal clock mode. In this state, the serial interface does not transmit/ receive data but only outputs the transmit clock from the SCK pin. When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state. If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait state is entered.
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HD404829R Series
External clock mode
STS wait state (Octal counter = 000, transmit clock disabled) 00 MCU reset
SMRA write
04 01 STS instruction 02 Transmit clock
06 SMRA write (IFS 1)
Transmit clock wait state (Octal counter = 000)
Transfer state (Octal counter = 000)
03 8 transmit clocks
05 STS instruction (IFS 1)
Internal clock mode
STS wait state (Octal counter = 000, transmit clock disabled)
SMRA write 18 Continuous clock output state (PMRA 0, 1 = 00)
10
MCU reset
13 SMRA write 14 11 STS instruction
8 transmit clocks
16 SMRA write (IFS 1)
Transmit clock 17
12 Transmit clock Transmit clock wait state (Octal counter = 000) 15 STS instruction (IFS 1) Transfer state (Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 71 Serial Interface State Transitions Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state, the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB: $028) to 0 or 1. The output level control example is shown in figure 72. Note that the output level cannot be controlled in transfer state.
86
,
Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMRA write SMRB write External clock selection Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined idle LSB IFS External clock mode Transmit clock wait state State STS wait state Transfer state MCU reset Port selection PMRA write SMRA write SMRB write Internal clock selection Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined idle LSB IFS Internal clock mode
HD404829R Series
Transmit clock wait state STS wait state
Dummy write for state transition Output level control in idle states
MSB
idle
Flag reset at transfer completion
STS wait state
Output level control in idle states
MSB
idle
Flag reset at transfer completion
Figure 72 Example of Serial Interface Operation Sequence
87

HD404829R Series
Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMRA write IFS = 1? Yes Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state State Transfer state SCK pin (input) Noise 1 2 3 4 5 SMRA write IFS
Transmit clock wait state Transfer state
6
7 8 Transfer state has been entered by the transmit clock error. When SMRA is written, IFS is set.
Flag set because octal counter reaches 000
Flag reset at transfer completion
Transmit clock error detection procedure
Figure 73 Transmit Clock Error Detection
88
HD404829R Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit clock error of this type can be detected as shown in figure 73. If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and therefore the error can be detected. Notes on Use: * Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode register A (SMRA: $005) again. * Serial interrupt request flag (IFS: $023, bit 2) set: If the state is changed from transfer to another by writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request flag, serial mode register A write or STS instruction execution must be programmed to be executed after confirming that the SCK pin is at 1, that is, after executing the input instruction to port R2. Registers for Serial Interface The serial interface operation is selected, and serial data is read and written by the following registers. Serial Mode Register A (SMRA: $005) Serial Mode Register B (SMRB: $028) Serial Data Register (SRL: $006, SRU: $007) Port Mode Register A (PMRA: $004) Miscellaneous Register (MIS: $00C) Serial Mode Register A (SMRA: $005): This register has the following functions (figure 74). * * * * R2 1/SCK pin function selection Transfer clock selection Prescaler division ratio selection Serial interface initialization
Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset. A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $023, bit 2) is set. Written data is valid from the second instruction execution cycle after the write operation, so the STS instruction must be executed at least two cycles after that.
89
HD404829R Series
Serial mode register A (SMRA: $005) Bit Initial value Read/Write Bit name 3 0 W SMRA3 2 0 W 1 0 W 0 0 W
SMRA2 SMRA1 SMRA0 Prescaler Clock source division ratio Prescaler Refer to table 23
SMRA3 0 1
R21/SCK mode selection R21 SCK
SMRA2 SMRA1 SMRA0 0 0 0 1 1 0 1 1 0 0 1 1 0 1
SCK Output
Output Input
System clock External clock
-- --
Figure 74 Serial Mode Register A (SMRA) Serial Mode Register B (SMRB: $028): This register has the following functions (figure 75). * Prescaler division ratio selection * Output level control in idle states Serial mode register B is a 2-bit write-only register. It cannot be written during data transfer. By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle states. The output level changes at the same time that SMRB1 is written to.
90
HD404829R Series
Serial mode register B (SMRB: $028) Bit Initial value Read/Write Bit name 3 -- -- 2 -- --
1 Undefined W
0 0 W SMRB0
Not used Not used SMRB1
SMRB1 0 1
Output level control in idle states Low level High level
SMRB0 0 1
Transmit clock division ratio Prescaler output divided by 2 Prescaler output divided by 4
Figure 75 Serial Mode Register B (SMRB) Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 76 and 77). * Transmission data write and shift * Receive data shift and read Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock. Input/output timing is shown in figure 78. Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the accuracy of the resultant data cannot be guaranteed.
Serial data register (lower digit) (SRL: $006) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR3 R/W SR2 R/W SR1 R/W SR0
Figure 76 Serial Data Register (SRL)
Serial data register (upper digit) (SRU: $007) Bit Initial value Read/Write Bit name
3 2 1 0
Undefined Undefined Undefined Undefined R/W SR7 R/W SR6 R/W SR5 R/W SR4
Figure 77 Serial Data Register (SRU)
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HD404829R Series
Transmit clock 1 Serial output data LSB 2 3 4 5 6 7 8 MSB
Serial input data latch timing
Figure 78 Serial Interface Output Timing Port Mode Register A (PMRA: $004): This register has the following functions (figure 79). * R2 2/SI pin function selection * R2 3/SO pin function selection Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.
Port mode register A (PMRA: $004) Bit Initial value Read/Write Bit name 3 -- -- 2 -- -- 1 0 W 0 0 W
Not used Not used PMRA1 PMRA0
PMRA1 0 1
R22/SI mode selection R22 SI
PMRA0 0 1
R23/SO mode selection R23 SO
Figure 79 Port Mode Register A (PMRA)
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HD404829R Series
Miscellaneous Register (MIS: $00C): This register has the following function (figure 80). * R2 3/SO pin PMOS control Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C) Bit Initial value Read/Write Bit name 3 0 W MIS3 2 0 W MIS2 1 0 W MIS1 0 0 W MIS0
MIS3 0 1 MIS2 0 1
Pull-up MOS on/off selection Off On
MIS1 0
MIS0 0
tRC 0.12207 ms 0.24414 ms
1 R23/SO PMOS on/off selection On 1 Off 1 0
7.8125 ms 31.25 ms Not used
Figure 80 Miscellaneous Register (MIS)
A/D Converter
The MCU has a built-in A/D converter that uses a successive approximation method with a resistor ladder. It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register.
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HD404829R Series
A/D interrupt request flag (IFAD) A/D mdoe register (AMR)
2
AN0 AN1 AN2 AN3
Selector
Encoder
A/D data register (ADR)
+ COMP -
A/D control logic
Conversion time control
A/D start flag (ADSF) Off in stop, watch, and subactive modes
AVCC AVSS
Resistance ladder Data bus Signal line
Figure 81 Block Diagram of A/D Converter A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion period, and bits 3 and 2 select a channel, as shown in figure 82.
94
Internal data bus
HD404829R Series
A/D mode register (AMR: $016) Bit Initial value Read/Write Bit name 3 0 W AMR3 2 0 W 1 -- -- 0 0 W AMR0
AMR2 Not used
AMR3 0 0 1 1
AMR2 0 1 0 1
Analog input selection AN0 AN1 AN2 AN3
AMR0 0 1
Conversion time 34tcyc 67tcyc
Figure 82 A/D Mode Register (AMR) A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and 85).
ADRU: $018 3 2 1 0 3 ADRL: $017 2 1 0
MSB Bit 7
LSB Bit 0
Figure 83 A/D Data Registers (ADRU, ADRL)
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HD404829R Series
A/D data register (lower digit) (ADRL: $017) Bit Initial value Read/Write Bit name 3 0 R ADRL3 2 0 R ADRL2 1 0 R ADRL1 0 0 R ADRL0
Figure 84 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018) Bit Initial value Read/Write Bit name 3 1 R ADRU3 2 0 R ADRU2 1 0 R 0 0 R
ADRU1 ADRU0
Figure 85 A/D Data Register Upper Digit (ADRU) A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is cleared. Refer to figure 86.
A/D start flag (ADSF: $020, bit 2) Bit Initial value Read/Write Bit name 3 0 R/W DTON DTON Refer to the description of operating modes 2 0 R/W ADSF 1 0 R/W WDON 0 0 R/W LSON WDON Refer to the description of timers
ADSF (A/D start flag) 1 0 A/D conversion started A/D conversion completed
LSON Refer to the description of operating modes
Figure 86 A/D Start Flag (ADSF)
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HD404829R Series
Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2), but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed. The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock. During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the power input.
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HD404829R Series
LCD Controller/Driver
The MCU has an LCD controller and driver which drive 4 common signal pins and 52 segment pins. The controller consists of a RAM area in which display data is stored, a display control register (LCR: $01B), and a duty-cycle/clock-control register (LMR: $01C) (figure 87). Four duty cycles and the LCD clock are programmable, and a built-in dual-port RAM ensures that display data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz oscillation clock is selected as the LCD clock source, the LCD can even be used in watch mode, in which the system clock stops.
VCC V1 COM1 COM2 COM3 COM4
Pin control Common signal output circuit
Internal LCD power supply switch
V2 V3 GND
LCD power supply control circuit
LCD control register (LCR) LCD output register 1 (LOR1) LCD output register 2 (LOR2) LCD output register 3 (LOR3)
4
3 SEG1 2
Display data Display control
SEG4
SEG5
Segment signal output circuit
52
Dual-port display RAM (52 digits)
SEG8
2
Clock
Duty selection
SEG9
SEG20
Selector
2 LCD mode register (LMR)
SEG21
CL0 CL1 CL2 CL3
SEG52
Data bus Clock line
Note:
Pin function switching circuit
Signal line
Figure 87 LCD Controller/Driver Block Diagram
98
Internal data bus
4
HD404829R Series
LCD Data Area and Segment Data ($050-$083): As shown in figure 88, each bit of the storage area corresponds to one of four duty cycles. If data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data.
RAM address $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05A $05B $05C $05D $05E $05F $060 $061 $062 $063 $064 $065 $066 $067 $068 $069 RAM address $06A $06B $06C $06D $06E $06F $070 $071 $072 $073 $074 $075 $076 $077 $078 $079 $07A $07B $07C $07D $07E $07F $080 $081 $082 $083
Bit 3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM4
Bit 2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM3
Bit 1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM2
Bit 0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM1
Bit 3 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM4
Bit 2 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM3
Bit 1 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM2
Bit 0 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM1
Figure 88 Configuration of LCD RAM Area (for Dual-Port RAM)
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HD404829R Series
LCD Control Register (LCR: $01B): Three-bit write-only register which controls LCD blanking, on/off switching of the liquid-crystal display's power supply division resistor, and display in watch and subactive modes, as shown in figure 89. * Blank/display Blank: Segment signals are turned off, regardless of LCD RAM data setting. Display: LCD RAM data is output as segment signals. * Power switch on/off Off: The power switch is off. On: The power switch is on and V1 is VCC. * Watch/subactive mode display Off: In watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. On: In watch and subactive modes, LCD RAM data is output as segment signals.
LCD display control register (LCR: $01B) Bit Initial value Read/Write Bit name 3 -- -- Not used 2 0 W LCR2 1 0 W LCR1 0 0 W LCR0 LCR1 0 1 LCR0 0 1 Power switch on/off Off On Blank/display Blank Display
LCR2 0 1
Display on/off selection in watch and subactive modes Off On
Figure 89 LCD Control Register (LCR)
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HD404829R Series
LCD Duty-Cycle/Clock Control Register (LMR: $01C): Four-bit write-only register which selects the display duty cycle and LCD clock source, as shown in figure 90. The dependence of frame frequency on duty cycle is listed in table 24.
LCD duty cycle/clock control register (LMR: $01C) Bit Initial value Read/Write Bit name 3 0 W LMR3 2 0 W LMR2 1 0 W LMR1 0 0 W LMR0
LMR3 0
LMR2 0
Input clock source selection CL0 (32.768-kHz x duty/64: when 32.768-kHz oscillation is used) CL1 (fOSC x duty cycle/1024) CL2 (fOSC x duty cycle/8192) CL3 (refer to table 24)
LMR1 0 0 1 1
LMR0 0 1 0 1
Duty cycle selection 1/4 duty 1/3 duty 1/2 duty Static
0 1 1
1 0 1
Figure 90 LCD Duty-Cycle/Clock Control Register (LMR)
101
HD404829R Series
Table 24 LCD Frame Frequencies for Different Duty Cycles
Frame Frequencies Duty Cycle Static LMR3 0 LMR2 0 1 1 0 1 CL0 CL1 CL2 CL3* 390.6 Hz 48.8 Hz 24.4 Hz 781.3 Hz 97.7 Hz 48.8 Hz fOSC = 400 kHz fOSC = 800 kHZ fOSC = 2 MHz 512 Hz 1953 Hz 244.1 Hz 122.1 Hz 64 Hz 1/2 0 0 1 1 0 1 CL0 CL1 CL2 CL3* 195.3 Hz 24.4 Hz 12.2 Hz 390.6 Hz 48.8 Hz 24.4 Hz 256 Hz 976.6 Hz 122.1 Hz 61 Hz 32 Hz 1/3 0 0 1 1 0 1 CL0 CL1 CL2 CL3* 130.2 Hz 16.3 Hz 8.1 Hz 260.4 Hz 32.6 Hz 16.3 Hz 170.7 Hz 651 Hz 81.4 Hz 40.7 Hz 21.3 Hz 1/4 0 0 1 1 0 1 CL0 CL1 CL2 CL3* 97.7 Hz 12.2 Hz 6.1 Hz 195.3 Hz 24.4 Hz 12.2 Hz 128 Hz 488.3 Hz 61 Hz 30.5 Hz 16 Hz Note: * The division ratio depends on the value of bit 3 of timer mode register A (TMA). Upper value: When TMA3 = 0, CL3 = f OSC x duty cycle/16384. Lower value: When TMA3 = 1, CL3 = 32.768 kHz x duty cycle/512. 976.6 Hz 122.1 Hz 61 Hz 1302 Hz 162.8 Hz 81.4 Hz 1953 Hz 244.1 Hz 122.1 Hz 3906 Hz 488.3 Hz 244.1 Hz fOSC = 4 MHz
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HD404829R Series
LCD Output Register 1 (LOR1: $01D): Write-only register used to specify ports R30-R33 as pins SEG1-SEG4 by individual pins (figure 91).
LCD output register 1 (LOR1: $01D) Bit Initial value Read/Write Bit name LOR13 0 1 LOR12 0 1 3 0 W LOR13 2 0 W LOR12 1 0 W LOR11 0 0 W LOR10 R31/SEG2 mode selection R31 SEG2 R30/SEG1 mode selection R30 SEG1
R33/SEG4 mode selection R33 SEG4 R32/SEG3 mode selection R32 SEG3
LOR11 0 1 LOR10 0 1
Figure 91 LCD Output Register 1 (LOR1) LCD Output Register 2 (LOR2: $01E): Write-only register used to specify ports R40-R43 as pins SEG5-SEG8 by individual pins (figure 92).
LCD output register 2 (LOR2: $01E) Bit Initial value Read/Write Bit name 3 0 W LOR23 2 0 W LOR22 1 0 W LOR21 0 0 W LOR20
LOR23 0 1 LOR22 0 1
R43/SEG8 mode selection R43 SEG8 R42/SEG7 mode selection R42 SEG7
LOR21 0 1 LOR20 0 1
R41/SEG6 mode selection R41 SEG6 R40/SEG5 mode selection R40 SEG5
Figure 92 LCD Output Register 2 (LOR2)
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HD404829R Series
LCD Output Register 3 (LOR3: $01F): Write-only register used to specify ports R5 0-R7 3 as pins SEG9- SEG20 in 4-pin units (figure 93).
LCD output register 3 (LOR3: $01F) Bit Initial value Read/Write Bit name 3 -- -- 2 0 W 1 0 W LOR31 0 0 W LOR30
Not used LOR32
LOR32 0 1
R70/SEG17-R73/SEG20 mode selection R70-R73 SEG17-SEG20
LOR30 0 1
R50/SEG9-R53/SEG12 mode selection R50-R53 SEG9-SEG12
LOR31 0 1
R60/SEG13-R63/SEG16 mode selection R60-R63 SEG13-SEG16
Figure 93 LCD Output Register 3 (LOR3) Large Liquid-Crystal Panel Drive and V LCD: To drive a large-capacity LCD, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 94. The size of these resistors cannot be simply calculated from the LCD load capacitance because the matrix configuration of the LCD complicates the paths of charge/discharge currents flowing through the capacitors--the resistance will also vary with lighting conditions. This size must be determined by trialand-error, taking into account the power dissipation of the device using the LCD, but a resistance of 1 to 10 k would usually be suitable. (Another effective method is to attach capacitors of 0.1 to 0.3 F.) Always turn off the power switch (set bit 1 of the LCR to 0) before changing the liquid-crystal drive voltage (VLCD).
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HD404829R Series
VCC (V 1 ) R V2 R V3 R GND C C R GND C R V3 R V2 VCC (V 1 )
VCC VCC VLCD
COM1
1
.
52
6-digit LCD with sign
V1 SEG1 V2 to V3 SEG52 GND Static drive
VCC VCC VLCD
COM1 COM2
2
.
52
13-digit LCD
V1 SEG1 V2 to V3 SEG52 GND
1/2 duty, 1/2 bias drive
VCC
VLCD
VCC COM1 to COM3 V1 V2 SEG1 to V3 GND SEG52
3
.
52
17-digit LCD with sign
1/3 duty, 1/3 bias drive
VCC
VCC COM1 to COM4 V
1
4
.
52
26-digit LCD
VLCD
V2 SEG1 to V3 GND SEG52
VCC V LCD GND
1/4 duty, 1/3 bias drive
Figure 94 LCD Connection Examples
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HD404829R Series
ZTATTM Microcomputer with Built-in Programmable ROM
Programming of Built-in programmable ROM The MCU can stop its function as an MCU in PROM mode for programming the built-in PROM. PROM mode is set up by setting the TEST, M0, and M1 terminals to "Low" level and the RESET terminal to "High" level. Writing and reading specifications of the PROM are the same as those for the commercial EPROM27256. Using a socket adapter for specific use of each product, programming is possible with a general-purpose PROM writer. Since an instruction of the HMCS400 series is 10 bits long, a conversion circuit is incorporated to adapt the general-purpose PROM writer. This circuit splits each instruction into five lower bits and five higher bits to write from or read to two addresses. This enables use of a general-purpose PROM. For instance, to write to a 16kword of built-in PROM with a general-purpose PROM writer, specify 32kbyte address ($0000-$7FFF). An example of PROM memory map is shown in figure 95. Notes: 1. When programming with a PROM writer, set up each ROM size to the address given in table b. If it is programmed erroneously to an address given in table 27 or later, check of writing of PROM may become impossible. Particularly, caution should be exercised in the case of a plastic package since reprogramming is impossible with it. Set the data in unused addresses to $FF. 2. If the indexes of the PROM writer socket, socket adapter and product are not aligned precisely, the product may break down due to overcurrent. Be sure to check that they are properly set to the writer before starting the writing process. 3. Two levels of program voltages (VPP) are available for the PROM: 12.5V and 21V. Our product employs a V PP of 12.5V. If a voltage of 21V is applied, permanent breakdown of the product will result. The VPP of 12.5V is obtained for the PROM writer by setting it according to the Intel 27258 specifications.
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HD404829R Series
Writing/verification
Programming of the built-in program ROM employs a high speed programming method. With this method, high speed writing is effected without voltage stress to the device or without damaging the reliability of the written data. A basic programming flow chart is shown in figure 96 and a timing chart in figure 97. For precautions for PROM writing procedure, refer to Section 2, "Characteristics of ZTATT M Microcomputer's Built-in Programmable ROM and precautions for its Applications." Table 25 Selection of Mode
Mode Writing Verification Prohibition of programming CE "Low" "High" "High" OE "High" "Low" "High" VPP VPP VPP VPP O0 - O 7 Data input Data output High impedance
Table 26 PROM Writer Program Address
ROM size 8k 12k 16k Address $0000 - $3FFF $0000 - $5FFF $0000 - $7FFF
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HD404829R Series
Programmable ROM (HD4074829)
The HD4074829 is a ZTAT TM microcomputer with built-in PROM that can be programmed in PROM mode. PROM Mode Pin Description
Pin No. FP-100B TFP-100B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 FP-100A 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MCU Mode Pin Name AV CC AN0 AN1 AN2 AN3 AV SS TEST OSC1 OSC2 RESET X1 X2 GND D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I O I I O GND CE OE VCC VCC I I VCC GND I I I I GND GND VCC I/O PROM Mode Pin Name VCC I/O Pin No. FP-100B TFP-100B 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 FP-100A 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 MCU Mode Pin Name D10 /STOPC D11 /INT0 R00/INT1 R01/INT2 R02/INT3 R03/INT4 R10/TOB R11/TOC R12/TOD R13/EVNB R20/EVND R21/SCK R22/SI R23/SO R30/SEG1 R31/SEG2 R32/SEG3 R33/SEG4 R40/SEG5 R41/SEG6 R42/SEG7 R43/SEG8 R50/SEG9 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A5 A6 A7 A8 A0 A10 A11 A12 A13 A14 O0 O1 O2 O3 O4 O5 O6 I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O PROM Mode Pin Name A9 VPP GND GND I/O I
Notes on next page.
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HD404829R Series
Pin No. FP-100B TFP-100B FP-100A 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 MCU Mode Pin Name PROM Mode Pin Name O7 O4 O3 O2 O1 O0 VCC A1 A2 A3 A4 I I I I Pin No. FP-100B TFP-100B 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 MCU Mode Pin Name SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 COM1 COM2 COM3 COM4 V1 V2 V3 VCC NUMO NUMO NUMG Note3 Note3 Note3 VCC PROM Mode Pin Name
I/O
I/O I/O I/O I/O I/O I/O I/O
FP-100A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2
I/O O O O O O O O O O O O O O O O O O O O O
I/O
R51/SEG10 I/O R52/SEG11 I/O R53/SEG12 I/O R60/SEG13 I/O R61/SEG14 I/O R62/SEG15 I/O R63/SEG16 I/O R70/SEG17 I/O R71/SEG18 I/O R72/SEG19 I/O R73/SEG20 I/O SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 O O O O O O O O O O O O O O O O
Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin 2. Each of O0-O4 has two pins; before using, each pair must be connected together. 3. NUMG and NUMO are not pins for user applications. Connect NUMG to the same potential as GND. Leave NUMO open.
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HD404829R Series
PROM Mode Pin Functions
VPP: Applies the programming voltage (12.5 V 0.3 V) to the built-in PROM. CE: Inputs a control signal to enable PROM programming and verification. OE : Inputs a data output control signal for verification. A0-A14: Act as address input pins of the built-in PROM. O0-O7: Act as data bus input pins of the built-in PROM. Each of O0-O4 has two pins; before using these pins, connect each pair together. M 0 , M1, RESET, TEST: Used to set PROM mode. The MCU is set to the PROM mode by pulling M0, M1, and TEST low, and RESET high. Other Pins (FP-100B/FP-100A): Connect pins 1/3 (AVCC), 8/10 (OSC1), 16/18 (D2), 17/19 (D3), 53/55 (R63/SEG16), and 97/99 (V CC ) to VCC, and pins 6/8 (AVSS) and 11/13 (X1) to GND. Leave other pins open.
$0000 $0001 . . . $001F $0020 . . . $007F $0080 . . . $1FFF $2000 1 1 1 1 1 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Lower 5 bits Upper 5 bits
$0000
Vector address
$000F $0010
Zero-page subroutine (64 words)
$003F $0040
Pattern (4,096 words)
$0FFF $1000
Program (16,384 words)
JMPL instruction (jump to RESET, STOPC routine) JMPL instruction (jump to INT 0 routine) JMPL instruction (jump to INT 1 routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B, INT2 routine) JMPL instruction (jump to timer C, INT3 routine) JMPL instruction (jump to timer D, INT4 routine) JMPL instruction (jump to A/D, serial routine)
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F
$7FFF
$3FFF
Upper three bits are not to be used (fill them with 111)
Figure 95 Memory Map in PROM Mode
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HD404829R Series
Start Set programming/verification modes V PP = 12.5 0.3 V, V CC = 6.0 0.25 V Address = 0 n=0 n + 1 n Program t PW =1 ms 5%
Yes No n < 25?
No
Verification OK? Yes Program t OPW = 3n ms
Address + 1 Address
Last address? Yes
No
Set read mode VCC = 5.0 0.5 V, V PP = V CC 0.6 V
No
All addresses read? Yes
Fail
End
Figure 96 Flowchart of High-Speed Programming
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HD404829R Series
Programming Electrical Characteristics
DC Characteristics (VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, T a = 25C 5C, unless otherwise specified)
Item Input high voltage level Input low voltage level Output high voltage level Output low voltage level Input leakage current VCC current VPP current Symbol VIH VIL VOH VOL I IL I CC I PP Pin(s) O0-O7, A0-A14, OE, CE O0-O7, A0-A14, OE, CE O0-O7 O0-O7 O0-O7, A0-A14, OE, CE Min 2.2 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max VCC + 0.3 0.8 -- 0.4 2 30 40 Unit V V V V A mA mA I OH = -200 A I OL = 1.6 mA Vin = 5.25 V/0.5 V Test Condition
AC Characteristics (VCC = 6.0 V 0.25 V, V PP = 12.5 V 0.3 V, Ta = 25C 5C, unless otherwise specified)
Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Program pulse width CE pulse width during overprogramming VCC setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF t VPS t PW t OPW t VCS t OE Min 2 2 2 0 2 -- 2 0.95 2.85 2 0 Typ -- -- -- -- -- -- -- 1.0 -- -- -- Max -- -- -- -- -- 130 -- 1.05 78.75 -- 500 Unit s s s s s ns s ms ms s ns Test Condition See figure 97
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HD404829R Series
Input pulse level: 0.8 V to 2.2 V Input rise/fall time: 20 ns Input timing reference levels: 1.0 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Programming Address t AS Data t DS V PP V CC V PP GND V CC GND t VPS t VCS Data in Stable t DH t AH Data out Valid t DF Verification
CE t PW OE t OPW t OES t OE
Figure 97 PROM Programming/Verification Timing
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HD404829R Series
Notes on PROM Programming Principles of Programming/Erasure: A memory cell in a ZTATTM microcomputer is the same as an EPROM cell; it is programmed by applying a high voltage between its control gate and drain to inject hot electrons into its floating gate. These electrons are stable, surrounded by an energy barrier formed by an SiO 2 film. The change in threshold voltage of a memory cell with a charged floating gate makes the corresponding bit appear as 0; a cell whose floating gate is not charged appears as a 1 bit (figure 98). The charge in a memory cell may decrease with time. This decrease is usually due to one of the following causes: * Ultraviolet light excites electrons, allowing them to escape. This effect is the basis of the erasure principle. * Heat excites trapped electrons, allowing them to escape. * High voltages between the control gate and drain may erase electrons. If the oxide film covering a floating gate is defective, the electron erasure rate will be greater. However, electron erasure does not often occur because defective devices are detected and removed at the testing stage.
Control gate SiO2 Source N+ N+ SiO2 Floating gate Drain Source N+ N+ Floating gate Drain Control gate
Write (0)
Erasure (1)
Figure 98 Cross-Sections of a PROM Cell PROM Programming: PROM memory cells must be programmed under specific voltage and timing conditions. The higher the programming voltage VPP and the longer the programming pulse t PW is applied, the more electrons are injected into the floating gates. However, if V PP exceeds specifications, the pn junctions may be permanently damaged. Pay particular attention to overshooting in the PROM programmer. In addition, note that negative voltage noise will produce a parasitic transistor effect that may reduce breakdown voltages. The ZTATTM microcomputer is electrically connected to the PROM programmer by a socket adapter. Therefore, note the following points: * Check that the socket adapter is firmly mounted on the PROM programmer. * Do not touch the socket adapter or the LSI during the programming. Touching them may affect the quality of the contacts, which will cause programming errors.
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HD404829R Series
PROM Reliability after Programming: In general, semiconductor devices retain their reliability, provided that some initial defects can be excluded. These initial defects can be detected and rejected by screening. Baking devices under high-temperature conditions is one method of screening that can rapidly eliminate data-hold defects in memory cells. (Refer to the previous Principles of Programming/Erasure section.) ZTATTM microcomputer devices are extremely reliable because they have been subjected to such a screening method during the wafer fabrication process, but Hitachi recommends that each device be exposed to 150C at one atmosphere for at least 48 hours after it is programmed, to ensure its best performance. The recommended screening procedure is shown in figure 99. Note: If programming errors occur continuously during PROM programming, suspend programming and check for problems in the PROM programmer or socket adapter. If programming verification indicates errors in programming or after high-temperature exposure, please inform Hitachi.
Programming, verification
Exposure to high temperature, without power 150C 10C, 48 h +8 h *
-0 h
Program read check VCC = 4.5 V or 5.5 V Note: * Exposure time is measured from when the temperature in the heater reaches 150C.
Figure 99 Recommended Screening Procedure
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HD404829R Series
Addressing Modes
RAM Addressing Modes The MCU has three RAM addressing modes, as shown in figure 100 and described below. Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.
W register W1 W0 X3 X register X2 X1 X0 Y3 Y register Y2 Y 1 Y0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Register Direct Addressing
1st word of Instruction Opcode d
9
2nd word of Instruction d8 d7 d6 d5 d4 d3 d2 d1 d0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Direct Addressing
Instruction Opcode 0 0 0 1 0 0 m3 m2 m1 m0
RAM address
AP9 AP8 AP7 AP6 AP5 AP4 AP3 AP2 AP1 AP0
Memory Register Addressing
Figure 100 RAM Addressing Modes
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HD404829R Series
ROM Addressing Modes and the P Instruction The MCU has four ROM addressing modes, as shown in figure 101 and described below. Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13-PC0) with 14-bit immediate data. Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program can branch to any address in the current page by executing the BR instruction. This instruction replaces the eight low-order bits of the program counter (PC7-PC0) with eight-bit immediate data. If the BR instruction is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next physical page, as shown in figure 98. This means that the execution of the BR instruction on a page boundary will make the program branch to the next page. Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages. Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000- $003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (PC5-PC0), and 0s are placed in the eight highorder bits (PC13-PC6). Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit immediate data, the accumulator, and the B register by executing the TBR instruction. P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction as shown in figure 102. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port output registers at the same time. The P instruction has no effect on the program counter.
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HD404829R Series
[JMPL] [BRL] [CALL] 1st word of instruction Opcode p3 p2 p1 p0 d9 d8 2nd word of instruction d7 d6 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Direct Addressing Instruction [BR] Opcode b7 b6 b5 b4 b3 b2 b1 b0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Current Page Addressing Instruction [CAL] 0 0 0 0 0 Opcode 0 0 0 d5 d4 d3 d2 d1 d0
Program counter
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 Zero Page Addressing Instruction
[TBR]
Opcode
p3
p2
p1
p0 B register B3 B2 B1 B0 A3 Accumulator A2 A1 A0
0 Program counter
0
PC13 PC12 PC11 PC10 PC 9 PC 8 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0
Table Data Addressing
Figure 101 ROM Addressing Modes
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HD404829R Series
Instruction [P] Opcode p3 p2 p1 p0 B3 0 0 B register B2 B1 B0 A3 Accumulator A2 A1 A0
Referenced ROM address RA13 RA12 RA11 RA10 RA 9 RA 8 RA 7 RA 6 RA 5 RA 4 RA 3 RA 2 RA 1 RA 0 Address Designation ROM data RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Accumulator, B register
B3
B2
B1
B0
A3 A
2
A1
A
0
If RO 8 = 1
ROM data
RO9 RO8 RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0
Output registers R1, R2
R23 R2 2 R21 R2 0 R13 R12 R11 R10 Pattern Output
If RO 9 = 1
Figure 102 P Instruction
256 (n - 1) + 255 BR AAA 256n
AAA
NOP
BR BR
AAA BBB
256n + 254 256n + 255 256 (n + 1)
BBB
NOP
Figure 103 Branching when the Branch Destination is on a Page Boundary
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HD404829R Series
Instruction Set
The MCU has 101 instructions, classified into the following 10 groups: * * * * * * * * * * Immediate instructions Register-to-register instructions RAM addressing instructions RAM register instructions Arithmetic instructions Compare instructions RAM bit manipulation instructions ROM addressing instructions Input/output instructions Control instructions
The functions of these instructions are listed in tables 27 to 36, and an opcode map is shown in table 37. Table 27 Immediate Instructions
Operation Load A from immediate Load B from immediate Load memory from immediate Mnemonic LAI i LBI i LMID i,d Operation Code 1 1 0 0 0 0 0 0 1 0 1 0 i3 i3 i2 i2 i1 i1 i0 i0 Function iA iB iM Words/ Status Cycles 1/1 1/1 2/2
0 1 1 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 1 i3 i2 i1 i0
Load memory LMIIY i from immediate, increment Y
i M, Y+1Y
NZ
1/1
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HD404829R Series
Table 28 Register-Register Instructions
Operation Load A from B Load B from A Load A from W Load A from Y Load A from SPX Load A from SPY Load A from MR Exchange MR and A Mnemonic LAB LBA LAW* LAY LASPX LASPY LAMR m XMRA m Operation Code 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 Function BA AB WA YA SPX A SPY A MR (m) A MR (m) A Words/ Status Cycles 1/1 1/1 2/2* 1/1 1/1 1/1 1/1 1/1
m3 m2 m1 m0 m3 m2 m1 m0
Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly.
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HD404829R Series
Table 29 RAM Address Instructions
Words/ Status Cycles 1/1 1/1 1/1 2/2* 1/1 1/1 NZ NB OVF NB 1/1 1/1 1/1 1/1 1/1 1/1 1/1
Operation Load W from immediate Load X from immediate Load Y from immediate Load W from A Load X from A Load Y from A Increment Y Decrement Y Add A to Y Subtract A from Y Exchange X and SPX Exchange Y and SPY Exchange X and SPX, Y and SPY
Mnemonic LWI i LXI i LYI i LWA LXA LYA IY DY AYY SYY XSPX XSPY XSPXY
Operation Code 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 i3 i3 0 0 1 1 1 1 0 0 0 0 0 0 i2 i2 0 0 0 0 1 1 1 1 0 0 0 i1 i1 i1 0 0 0 0 0 1 0 0 0 1 1 i0 i0 i0 0 0 0 0 0 1 0 0 1 0 1
Function iW iX iY AW AX AY Y+1Y Y-1Y Y+AY Y-AY X SPX Y SPY X SPX, Y SPY
Note: * Although the LAW and LWA instructions require an operand ($000) in the second word, the assembler generates it automatically and thus there is no need to specify it explicitly.
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HD404829R Series
Table 30 RAM Register Instructions
Operation Load A from memory Mnemonic LAM LAMX LAMY LAMXY Operation Code 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Function MA M A, X SPX M A, Y SPY M A, X SPX, Y SPY MA MB M B, X SPX M B, Y SPY M B, X SPX, Y SPY AM A M, X SPX A M, Y SPY A M, X SPX, Y SPY AM 2/2 1/1 2/2 1/1 Words/ Status Cycles 1/1
Load A from memory Load B from memory
LAMD d LBM LBMX LBMY LBMXY
0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1
Load memory from A
LMA LMAX LMAY LMAXY
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 1 1
0 1 0 1
Load memory from A
LMAD d
0110010000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
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HD404829R Series
Table 30 RAM Register Instructions (cont)
Operation Load memory from A, increment Y Mnemonic LMAIY Operation Code 0 0 0 1 0 1 0 0 0 0 Function A M, Y+1Y A M, Y + 1 Y, X SPX A M, Y-1Y A M, Y - 1 Y, X SPX MA 1/1 NB 1/1 Words/ Status Cycles NZ 1/1
LMAIYX
0
0
0
1
0
1
0
0
0
1
Load memory from A, decrement Y
LMADY
0
0
1
1
0
1
0
0
0
0
LMADYX
0
0
1
1
0
1
0
0
0
1
Exchange memory and A
XMA
0
0
1
0
0
0
0
0
0
0
XMAX XMAY XMAXY
0 0 0
0 0 0
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
1 0 1
M A, X SPX M A, Y SPY M A, X SPX, Y SPY MA 2/2
Exchange memory and A Exchange memory and B
XMAD d
0110000000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 0 0 0 0 0 0
XMB
MB
1/1
XMBX XMBY XMBXY
0 0 0
0 0 0
1 1 1
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 1 1
1 0 1
M B, X SPX M B, Y SPY M B, X SPX, Y SPY
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HD404829R Series
Table 31 Arithmetic Instructions
Operation Mnemonic Operation Code 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 i3 1 1 0 1 i2 1 1 1 0 i1 0 1 1 1 i0 0 1 0 0 Function A+iA B+1B B-1B Status OVF NZ NB Words/ Cycles 1/1 1/1 1/1 1/1 1/1
Add immediate to AI i A Increment B Decrement B IB DB
Decimal DAA adjust for addition Decimal adjust for subtraction Negate A Complement B Rotate right A with carry Rotate left A with carry Set carry Reset carry Test carry DAS
NEGA COMB ROTR ROTL SEC REC TC
0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 1 1 1 0 0
1 1 0 0 1 1 1 0
1 0 1 1 1 1 1 0
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 0
0 0 0 0 1 0 1 0
0 0 0 1 1 0 1 0
A+1A BB
1/1 1/1 1/1 1/1
1 CA 0 CA CA M+AA M+AA OVF OVF
1/1 1/1 1/1 1/1 2/2 1/1 2/2 1/1
Add A to memory AM Add A to memory AMD d Add A to memory AMC with carry Add A to memory AMCD d with carry Subtract A from memory with carry Subtract A from memory with carry OR A and B SMC
0100001000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 1 0 0 0
M + A + CA A OVF OVF CA M + A + CA A OVF OVF CA M - A - CA A NB NB CA M - A - CA A NB NB CA ABA
0100011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 1 1 0 0 0
SMCD d
0110011000 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 0 0 1 0 0
2/2
OR
1/1
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HD404829R Series
Table 31 Arithmetic Instructions (cont)
Operation AND memory with A AND memory with A OR memory with A OR memory with A EOR memory with A EOR memory with A Mnemonic ANM ANMD d ORM ORMD d EORM EORMD d Operation Code 0 0 1 0 0 1 1 1 0 0 Function A MA A MA A MA A MA A M A A M A Words/ Status Cycles NZ NZ NZ NZ NZ NZ 1/1 2/2 1/1 2/2 1/1 2/2
0110011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 1 0 0
0100001100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 1 1 0 0
0100011100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
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HD404829R Series
Table 32 Compare Instructions
Operation Immediate not equal to memory Immediate not equal to memory A not equal to memory A not equal to memory B not equal to memory Y not equal to immediate Immediate less or equal to memory Immediate less or equal to memory A less or equal to memory A less or equal to memory B less or equal to memory A less or equal to immediate Mnemonic INEM i Operation Code 0 0 0 0 1 0 i3 i2 i1 i0 Function iM Words/ Status Cycles NZ 1/1
INEMD i, d
0 1 0 0 1 0 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 1 0 0
iM
NZ
2/2
ANEM ANEMD d BNEM YNEI i ILEM i
AM AM BM Yi iM
NZ NZ NZ NZ NB
1/1 2/2 1/1 1/1 1/1
0100000100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 i3 i3 1 i2 i2 0 i1 i1 0 i0 i0
ILEMD i, d
0 1 0 0 1 1 i3 i2 i1 i0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 1 0 1 0 0
iM
NB
2/2
ALEM
AM
NB
1/1
ALEMD d
0100010100 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 1 0 0 0 1 0 0
AM
NB
2/2
BLEM
BM
NB
1/1
ALEI i
1
0
1
0
1
1
i3
i2
i1
i0
Ai
NB
1/1
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HD404829R Series
Table 33 RAM Bit Manipulation Instructions
Operation Set memory bit Set memory bit Reset memory bit Reset memory bit Test memory bit Test memory bit Mnemonic SEM n SEMD n,d REM n REMD n,d TM n TM n,d Operation Code 0 0 1 0 0 0 0 1 n1 n0 Function i M (n) i M (n) 0 M (n) 0 M (n) M (n) M (n) Status Words/ Cycles 1/1 2/2 1/1 2/2 1/1 2/2
0 1 1 0 0 0 0 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 0 n1 n0
0 1 1 0 0 0 1 0 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 0 0 0 1 1 n1 n0
0 1 1 0 0 0 1 1 n1 n0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Table 34 ROM Addressing Instructions
Operation Branch on status 1 Long branch on status 1 Long jump unconditionally Subroutine jump on status 1 Long subroutine jump on status 1 Table branch Return from subroutine Return from interrupt Mnemonic BR b BRL u JMPL u CAL a CALL u TBR p RTN RTNI Operation Code 1 1 b7 b6 b5 b4 b3 b2 b1 b0 Function Words/ Status Cycles 1 1 1/1 2/2 2/2 1 1 1 1/2 2/2 1/1 1/3 1 IE, ST carry restored 1/3
0 1 0 1 1 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 1 a5 a4 a3 a2 a1 a0
0 1 0 1 1 0 p3 p2 p1 p0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 p3 p2 p1 p0 0 0 0 0 0 0 0 1
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Table 35 Input/Output Instructions
Operation Set discrete I/O latch Set discrete I/O latch direct Reset discrete I/O latch Reset discrete I/O latch direct Test discrete I/O latch Test discrete I/O latch direct Load A from R-port register Load B from R-port register Load R-port register from A Load R-port register from B Pattern generation Mnemonic SED SEDD m Operation Code 0 1 0 0 1 1 1 1 1 1 0 0 0 1 0 0 Function 1 D (Y) 1 D (m) Words/ Status Cycles 1/1 1/1
m3 m2 m1 m0
RED REDD m
0 1
0 0
0 0
1 1
1 1
0 0
0
1
0
0
0 D (Y) 0 D (m)
1/1 1/1
m3 m2 m1 m0
TD TDD m LAR m
0 1 1
0 0 0
1 1 0
1 0 1
1 1 0
0 0 1
0
0
0
0
D (Y) D (m) R (m) A
1/1 1/1 1/1
m3 m2 m1 m0 m3 m2 m1 m0
LBR m
1
0
0
1
0
0
m3 m2 m1 m0
R (m) B
1/1
LRA m
1
0
1
1
0
1
m3 m2 m1 m0
A R (m)
1/1
LRB m
1
0
1
1
0
0
m3 m2 m1 m0
B R (m)
1/1
Pp
0
1
1
0
1
1
p3 p2 p1 p0
1/2
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HD404829R Series
Table 36 Control Instructions
Operation No operation Start serial Standby mode/Watch mode* Stop mode/ Watch mode Mnemonic NOP STS SBY Operation Code 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 Function Words/ Status Cycles 1/1 1/1 1/1
STOP
0
1
0
1
0
0
1
1
0
1
1/1
Note: * Only on return from subactive mode.
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Table 37 Opcode Map
R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction
TD LWI i(2) LBI i(4) LYI i(4) LXI i(4) LAI i(4) LBR m(4) LAR m(4) REDD m(4) LAMR m(4) AI i(4) LMIIY i(4) TDD m(4) ALEI i(4) LRB m(4) LRA m(4) SEDD m(4) XMRA m(4) XMB(XY) LMADY(X) BLEM SYY SED XMA(XY) LAM(XY) ROTR ROTL SEM n(2) LMA(XY) DAA TBR p(4) LBA LYA LXA REC DB DY SEC SMC DAS NEGA LBM(XY) LMAIY(X) BNEM AYY RED
0 0
NOP RTN
L
1
RTNI
2
3
4
ALEM
5
6
7
8
AM AMC
9
A
B
C
ORM EORM
D
E
F
XSPX XSPY XSPXY ANEM
INEM i(4) ILEM i(4) LAB LASPY LASPX YNEI i(4) REM n(2) ANM LAY TM n(2) IB IY TC
RAM direct address instruction (2-word/2-cycle)
2-word/2-cycle instruction
131
HD404829R Series
Table 37 Opcode Map (cont)
R8 R9 H 0 1 2 3 4 5 6 0 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 1 8 9 A B C D E F 1-word/2-cycle instruction 1-word/3-cycle instruction RAM direct address instruction (2-word/2-cycle) 2-word/2-cycle instruction
BR b(8) CAL a(6) XMAD LAMD LMAD SEMD n(2) SMCD LMID i(4) P p(4) COMB OR
1 0
LAW LWA
L
1
2
3
4
ANEMD ALEMD
5
6
7
8
AMD AMCD
9
A
B
C
ORMD
EORMD
D
E
F
INEMD i(4) ILEMD i(4) STS JMPL p(4) CALL p(4) BRL p(4) REMD n(2) ANMD TMD n(2) SBY STOP
132
HD404829R Series
Absolute Maximum Ratings
Item Supply voltage Programming voltage Pin voltage Total permissible input current Total permissible output current Maximum input current Symbol VCC VPP VT Io -Io Io -I o Topr Tstg Value -0.3 to +7.0 -0.3 to +14.0 -0.3 to VCC + 0.3 100 50 4 30 Maximum output current Operating temperature Storage temperature 4 -20 to +75 -55 to +125 Unit V V V mA mA mA mA mA C C 2 3 4, 5 4, 6 7, 8 1 Notes
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to D 11 (VPP) of the HD4074829. 2. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to ground. 3. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 4. The maximum input current is the maximum current flowing from each I/O pin to ground. 5. Applies to R0-R7. 6. Applies to D 0-D 9. 7. The maximum output current is the maximum current flowing out from V CC to each I/O pin. 8. Applies to D 0-D 9 and R0-R7.
133
HD404829R Series
Electrical Characteristics
DC Characteristics (HD404828R, HD4048212R, HD404829R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified)
Item Input high voltage Symbol VIH Pin(s) RESET, SCK, SI, INT0, INT1 INT2, INT3, INT4, STOPC, EVNB, EVND OSC1 Input low voltage VIL RESET, SCK, SI, INT0, INT1, INT2, INT3, INT4, STOPC, EVNB, EVND OSC1 Output high voltage Output low voltage I/O leakage current VOH VOL II L SCK, SO, TOB, TOC, TOD SCK, SO, TOB, TOC, TOD RESET, SCK, SI, INT0, INT1, INT2, INT3, INT4, STOPC, EVNB, EVND, OSC1, TOB, TOC, TOD, SO VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) ICC2 VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) Current dissipation in standby mode ISBY1 VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) ISBY2 VCC Min 0.9VCC Typ -- Max VCC + 0.3 Unit V Test Condition -- Notes
VCC - 0.3 -0.3
-- --
VCC + 0.3 0.1VCC
V V
External clock operation --
-0.3 VCC - 1.0 -- --
-- -- -- --
0.3 -- 0.4 1.0
V V V A
External clock operation -I OH = 0.5 mA IOL = 0.4 mA Vin = 0 V to V CC 1
Current dissipation in active mode
ICC1
--
2.5
5.0
mA
VCC = 5.0 V, fOSC = 4 MHz
2
-- --
5 0.3
9 0.9 mA VCC = 3.0 V, fOSC = 800 kHz 2
-- --
0.6 1.0
1.8 2.0 mA VCC = 5.0 V, fOSC = 4 MHz, LCD on 3
-- --
1.2 0.2
3 0.7 mA VCC = 3.0 V, fOSC = 800 kHz, LCD on 3
Notes on next page.
134
HD404829R Series
Item Current dissipation in subactive mode Symbol ISUB Pin(s) VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) Current dissipation in watch mode IWTC1 VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) IWTC2 VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) Current dissipation in stop mode ISTOP VCC (HD404828R, HD4048212R, HD404829R) VCC (HD4074829) Stop mode retaining voltage VSTOP VCC Min -- Typ 25 Max 70 Unit A Test Condition VCC = 3.0 V, LCD on 32-kHz oscillator VCC = 3.0 V, LCD on 32-kHz oscillator VCC = 3.0 V, LCD on 32-kHz oscillator Notes 4
--
70
150
A
4
--
15
40
A
4
-- --
18 5
40 10 A VCC = 3.0 V, LCD off 32-kHz oscillator 4
-- --
8 0.5
15 5 A VCC = 3.0 V, No 32-kHz oscillator 4
-- 2
1 --
10 -- V No 32-kHz oscillator 5
Notes: 1. Output buffer current is excluded. 2. I CC1 and I CC2 are the source currents when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET at V CC (VCC - 0.3 V to VCC) TEST at V CC (VCC - 0.3 V to VCC) 3. I SBY1 and I SBY2 are the source currents when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Serial interface stopped Standby mode Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) 4. These are the source currents when no I/O current is flowing. Test conditions: Pins: RESET at GND (0 V to 0.3 V) TEST at V CC (VCC - 0.3 V to VCC) D11 (VPP) at VCC (VCC - 0.3 V to VCC) for the HD4074829 5. The required voltage for RAM data retention.
135
HD404829R Series
I/O Characteristics for Standard Pins (HD404828R, HD4048212R, HD404829R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Symbol VIH VIL VOH VOL II L Pin(s) D10 , D11 , R0-R7 D10 , D11 , R0-R7 R0-R7 R0-R7 D10 , R0-R7 D11 (HD404828R, HD4048212R, HD404829R) D11 (HD4074829) Min 0.7VCC -0.3 VCC - 1.0 -- -- -- Typ -- -- -- -- -- -- Max VCC + 0.3 0.3VCC -- 0.4 1 1 Unit V V V V A A Test Condition -- -- -I OH = 0.5 mA IOL = 0.4 mA Vin = 0 V to V CC Vin = 0 V to V CC 1 1 Notes
-- --
-- -- 30
1 20 90
A A A
Vin = VCC - 0.3 V to VCC Vin = 0 V to 0.3 V VCC = 3.0 V, Vin = 0 V
1 1
Pull-up MOS current
-I PU
R0-R7
5
Note: 1. Output buffer current is excluded.
I/O Characteristics for High-Current Pins (HD404828R, HD4048212R, HD404829R: V CC = 2.7 to 6.0 V, GND = 0 V, T a = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Input high voltage Input low voltage Output high voltage Output low voltage I/O leakage current Pull-up MOS current II L -I PU D0-D9 D0-D9 Symbol VIH VIL VOH VOL Pin(s) D0-D9 D0-D9 D0-D9 D0-D9 Min 0.7VCC -0.3 VCC - 1.0 -- -- -- 5 Typ -- -- -- -- -- -- 30 Max VCC + 0.3 0.3VCC -- 0.4 2.0 1 90 Unit V V V V V A A Test Condition -- -- -I OH = 0.5 mA IOL = 0.4 mA IOL = 15 mA, VCC = 4.5 V to 6.0 V Vin = 0 V to V CC VCC = 3 V, Vin = 0 V 1 2 Notes
Note: 1. The test condition of HD4074829 is VCC = 4.5 V to 5.5 V. 2. Output buffer current is excluded.
136
HD404829R Series
LCD Circuit Characteristics (HD404828R, HD4048212R, HD404829R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, T a = -20C to +75C, unless otherwise specified)
Item Segment driver voltage drop Common driver voltage drop LCD power supply division resistance Symbol VDS VDC RW Pin(s) SEG1-SEG52 COM1-COM4 -- (HD404828R, HD4048212R, HD404829R) -- (HD4074829) LCD voltage VLCD V1 Min -- -- 50 Typ -- -- 300 Max 0.6 0.3 900 Unit V V k Test Condition IPD = 3 A IPD = 3 A Between V 1 and GND Notes 1 1
100 2.7
300 --
900 VCC
k V
-- -- 2
Notes: 1. VDS and VDC are the voltage drops from power supply pins V1, V2, V3, and GND to each segment pin and each common pin, respectively. 2. When VLCD is supplied from an external source, the following relations must be retained: VCC V1 V2 V3 GND
A/D Converter Characteristics (HD404828R, HD4048212R, HD404829R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Analog power voltage Analog input voltage Current between AV CC and AVSS Symbol AV CC AV in I AD Pin(s) AV CC AN0-AN 3 -- (HD404828R, HD4048212R, HD404829R) -- (HD4074829) Analog input capacitance Resolution Number of inputs Absolute accuracy Conversion time Input impedance CAin -- -- -- -- -- AN0-AN 3 -- -- -- -- AN0-AN 3 Min VCC - 0.3 AV SS -- Typ VCC -- -- Max VCC + 0.3 AV CC 250 Unit V V A Test Condition -- -- VCC = AVCC = 5.0 V Notes 1
-- -- 8 0 -- 34 1
50 15 8 -- -- -- --
150 -- 8 4 2.0 67 -- pF Bit Channel LSB tcyc M -- -- -- Ta = 25C, VCC = 4.5-5.5 V -- fOSC = 1 MHz, Vin = 0.0 V
137
HD404829R Series
AC Characteristics (HD404828R, HD4048212R, HD404829R: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Clock oscillation frequency 0.4 X1, X2 Instruction cycle time tsubcyc -- tcyc -- -- 0.95 2 -- -- Oscillation stabilization time tRC OSC1, OSC2 OSC1, OSC2 X1, X2 External clock high width External clock low width External clock rise time External clock fall time INT0-INT4, EVNB , tI H EVND high widths INT0-INT4, EVNB , tI L EVND low widths RESET high width STOPC low width RESET fall time STOPC rise time Input capacitance tRSTH tSTPL tRSTf tSTPr Cin INT0-INT4, EVNB, EVND INT0-INT4, EVNB, EVND RESET STOPC RESET STOPC All pins except D 11 tCPf OSC1 tCPr OSC1 tCPL OSC1 tCPH OSC1 -- -- -- 100 215 100 215 -- -- -- -- 2 2 2 1 -- -- -- -- 32.768 -- -- 244.14 122.07 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 -- 10 10 -- -- 7.5 30 3 -- -- -- -- 20 35 20 35 -- -- -- -- 20 20 15 MHz kHz s s s s ms ms s ns ns ns ns ns ns ns ns tcyc / tsubcyc tcyc / tsubcyc tcyc tRC ms ms pF Symbol fOSC Pin(s) OSC1, OSC2 Min 0.4 Typ -- Max 4.2 Unit MHz Test Condition 1/4 division VCC=3.0V-6.0V 1/4 division VCC=2.7V-6.0V -- VCC=3.0V-6.0V VCC=2.7V-6.0V 32-kHz oscillator, 1/8 division 32-kHz oscillator, 1/4 division Ceramic oscillator Crystal oscillator VCC=3.0V-6.0V Ta = -10C to +60C VCC=3.0V-6.0V VCC=2.7V-6.0V VCC=3.0V-6.0V VCC=2.7V-6.0V VCC=3.0V-6.0V VCC=2.7V-6.0V VCC=3.0V-6.0V VCC=2.7V-6.0V -- -- -- -- -- -- f = 1 MHz Vin = 0 V, 2 2 2 3 3 3 3 3 3 3 3 4 4 5 6 5 6 1 1 Notes
Notes on next page.
138
HD404829R Series
Notes: 1. With a crystal oscillator, Vcc=3.0V to 6.0V. 2. There are three oscillator stabilization times. (1) At power on, the time between the point where Vcc reaches 2.7V and the point where oscillation has stabilized. (2) At clearing stop mode, the time between the point where the RESET pin reaches the high level and the point where oscillation has stabilized. (3) At clearing stop mode, the time between the point where the STOPC pin reaches the low level and the point where oscillation has stabilized. At power on or when stop mode is cleared, RESET or STOPC must be input for at least t RC to ensure the oscillation stabilization time. Since the oscillator stabilization time will depend on circuit constants and stray capacitances, determine the oscillator by consulting with the oscillator's manufacturer. Be sure to set miscellaneous register (MIS) bits MIS1 and MIS0 to match the system clock oscillator stabilization time. 3. Refer to figure 99. 4. Refer to figure 100. The t cyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. 5. Refer to figure 101. 6. Refer to figure 102.
139
HD404829R Series
AC Characteristics (HD4074829: V CC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified)
Item Clock oscillation frequency Symbol fOSC Pin(s) OSC1, OSC2 Min 0.4 0.4 0.4 X1, X2 Instruction cycle time tcyc -- -- 0.95 1 2 tsubcyc -- -- -- Oscillation stabilization time tRC OSC1, OSC2 OSC1, OSC2 X1, X2 External clock high width tCPH OSC1 -- -- -- 100 105 215 External clock low width tCPL OSC1 100 105 215 External clock rise time tCPr OSC1 -- -- External clock fall time tCPf OSC1 -- -- INT0-INT4, EVNB , EVND high widths INT0-INT4, EVNB , EVND low widths RESET high width STOPC low width RESET fall time STOPC rise time Input capacitance tI H tI L tRSTH tSTPL tRSTf tSTPr Cin INT0-INT4, 2 EVNB, EVND INT0-INT4, 2 EVNB, EVND RESET STOPC RESET STOPC All pins except D 11 D11 2 1 -- -- -- -- Typ -- -- -- 32.768 -- -- -- 244.14 122.07 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 4.2 4.0 2.0 -- 10 10 10 -- -- 7.5 30 3 -- -- -- -- -- -- 20 35 20 35 -- -- -- -- 20 20 15 180 Unit MHz MHz MHz kHz s s s s s ms ms s ns ns ns ns ns ns ns ns ns ns tcyc / tsubcyc tcyc / tsubcyc tcyc tRC ms ms pF pF Test Condition 1/4 division VCC=4.5V-5.5V 1/4 division VCC=3.5V-5.5V 1/4 division VCC=2.7V-5.5V -- VCC=4.5V-5.5V VCC=3.5V-5.5V VCC=2.7V-5.5V 32-kHz oscillator, 1/8 division 32-kHz oscillator, 1/4 division Ceramic oscillator Crystal oscillator VCC=3.0V-5.5V Ta = -10C to+60C VCC=4.5V-5.5V VCC=3.5V-5.5V VCC=2.7V-5.5V VCC=4.5V-5.5V VCC=3.5V-5.5V VCC=2.7V-5.5V VCC=3.5V-5.5V VCC=2.7V-5.5V VCC=3.5V-5.5V VCC=2.7V-5.5V -- -- -- -- -- -- f = 1 MHz, Vin = 0 V f = 1 MHz, Vin = 0 V 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 5 6 5 6 1 1 Notes
Notes on next page.
140
HD404829R Series
Notes: 1. With a crystal oscillator, VCC=3.0V to 5.5V. 2. There are three oscillator stabilization times. (1) At power on, the time between the point where VCC reaches 2.7V and the point where oscillation has stabilized. (2) At clearing stop mode, the time between the point where the RESET pin reaches the high level and the point where oscillation has stabilized. (3) At clearing stop mode, the time between the point where the STOPC pin reaches the low level and the point where oscillation has stabilized. At power on or when stop mode is cleared, RESET or STOPC must be input for at least t RC to ensure the oscillation stabilization time. Since the oscillator stabilization time will depend on circuit constants and stray capacitances, determine the oscillator by consulting with the oscillator's manufacturer. Be sure to set miscellaneous register (MIS) bits MIS1 and MIS0 to match the system clock oscillator stabilization time. 3. Refer to figure 99. 4. Refer to figure 100. The t cyc unit applies when the MCU is in standby or active mode. The t subcyc unit applies when the MCU is in watch or subactive mode. 5. Refer to figure 101. 6. Refer to figure 102.
141
HD404829R Series
Serial Interface Timing Characteristics (HD404828R, HD4048212R, HD404829R: V CC = 2.7 to 6.0 V, GND = 0 V, Ta = -20C to +75C; HD4074829: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = -20C to +75C, unless otherwise specified) During Transmit Clock Output
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tScyc tSCKH tSCKL tSCKr tSCKf tDSO tSSI tHSI Pin SCK SCK SCK SCK SCK SO SI SI Min 1.0 0.5 0.5 -- -- -- 300 300 Typ -- -- -- -- -- -- -- -- Max -- -- -- 200 200 500 -- -- Unit tcyc tScyc tScyc ns ns ns ns ns Test Condition Load shown in figure 104 Load shown in figure 104 Load shown in figure 104 Load shown in figure 104 Load shown in figure 104 Load shown in figure 104 -- -- Notes 1 1 1 1 1 1 1 1
Note: 1. Refer to figure 103.
During Transmit Clock Input
Item Transmit clock cycle time Transmit clock high width Transmit clock low width Transmit clock rise time Transmit clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tScyc tSCKH tSCKL tSCKr tSCKf tDSO tSSI tHSI Pin SCK SCK SCK SCK SCK SO SI SI Min 1.0 0.5 0.5 -- -- -- 300 300 Typ -- -- -- -- -- -- -- -- Max -- -- -- 200 200 500 -- -- Unit tcyc
tScyc
Test Condition -- -- -- -- -- Load shown in figure 104 -- --
Notes 1 1 1 1 1 1 1 1
tScyc ns ns ns ns ns
Note: 1. Refer to figure 103.
142
HD404829R Series
OSC1 1/fCP VCC - 0.3 V 0.3 V tCPH tCPr tCPf tCPL
Figure 104 External Clock Timing
INT0 to INT4, EVNB, EVND 0.9VCC 0.1VCC
tIH
tIL
Figure 105 Interrupt Timing
RESET 0.9VCC 0.1VCC tRSTH tRSTf
Figure 106
Reset Timing
143
HD404829R Series
STOPC 0.9VCC 0.1VCC tSTPL tSTPr
Figure 107
STOPC Timing
t Scyc
t SCKf SCK VCC - 1.0 V (0.9VCC )* 0.4 V (0.1VCC)* t DSO SO t SCKL
t SCKr t SCKH
VCC - 1.0 V 0.4 V t SSI t HSI
SI
0.9V CC 0.1VCC
Note: * VCC - 1.0 V and 0.4 V are the threshold voltages for transmit clock output, and 0.9VCC and 0.1VCC are the threshold voltages for transmit clock input.
Figure 108 Serial Interface Timing
VCC RL = 2.6 k Test point C= 30 pF R= 12 k 1S2074 H or equivalent
Figure 109 Timing Load Circuit
144
HD404829R Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version (HD404829R). A 16-kword data size is required to change ROM data to mask manufacturing data since the program used is for a 16-kword version. This limitation applies when using an EPROM or a data base.
ROM 8-kword version: HD404828R Address $2000-$3FFF ROM 12-kword version: HD4048212R Address $3000-$3FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (8,192 words) $1FFF $2000 Not used $3FFF
$0000 Vector address $000F $0010 Zero-page subroutine (64 words) $003F $0040 Pattern & program (12,288 words) $2FFF $3000 Not used $3FFF
Fill this area with 1s
145
HD404829R Series
HD404829R/HD404828R/HD4048212R Option List
Please check off the appropriate applications and enter the necessary information.
Date of order Customer Department Name ROM code name LSI number (Hitachi entry) / /
1. ROM Size
HD404828R HD4048212R HD404829R 8-kword 12-kword 16-kword
2. Optional Function
* * With 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, with time-base for clock Without 32-kHz CPU operation, without time-base for clock Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).
3. ROM Code Data Type Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTATTM version).
The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMs.
4. System Oscillator (OSC1 and OSC2)
Ceramic oscillator Crystal oscillator External clock f= f= f= MHz MHz MHz
5. Stop Mode
Used Not used
6. Package
FP-100A FP-100B TFP-100B
146
HD404829R Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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